ADSP-2183–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
B Grade
Parameter
Min
Max
Min
Max
Unit
VDD
Supply Voltage
3.0
3.6
3.0
3.6
V
TAMB
Ambient Operating Temperature
0
+70
–40
+85
°C
ELECTRICAL CHARACTERISTICS
K/B Grades
Parameter
Test Conditions
Min
Typ
Max
Unit
VIH
Hi-Level Input Voltage
1, 2
@ VDD = max
2.0
V
VIL
Lo-Level Input Voltage1, 3
@ VDD = min
0.4
V
VOH
Hi-Level Output Voltage
1, 4, 5
@ VDD = min
IOH = –0.5 mA
2.4
V
@ VDD = min
IOH = –100
A6
VDD – 0.3
V
VOL
Lo-Level Output Voltage
1, 4, 5
@ VDD = min
IOL = 2 mA
0.4
V
IIH
Hi-Level Input Current
3
@ VDD = max
VIN = VDD max
10
A
IIL
Lo-Level Input Current3
@ VDD = max
VIN = 0 V
10
A
IOZH
Three-State Leakage Current
7
@ VDD = max
VIN = VDD max
8
10
A
IOZL
Three-State Leakage Current
7
@ VDD = max
VIN = 0 V
8
A
IDD
Supply Current (Idle)9, 10
@ VDD = 3.3
TAMB = +25
°C
tCK = 19 ns
11
10
mA
tCK = 25 ns
11
9mA
tCK = 30 ns
11
8mA
tCK = 34.7 ns
11
6mA
IDD
Supply Current (Dynamic)
10, 12
@ VDD = 3.3
TAMB = +25
°C
tCK = 19 ns
11
44
mA
tCK = 25 ns
11
35
mA
tCK = 30 ns
11
30
mA
tCK = 34.7 ns
11
26
mA
CI
Input Pin Capacitance
3, 6, 13
@ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = +25
°C8
pF
CO
Output Pin Capacitance
6, 7, 13, 14
@ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = +25
°C8
pF
NOTES
1Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD0–IAD15, PF0–PF7.
12Input only pins:
RESET, IRQ2, BR, MMAP, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL.
13Input only pins: CLKIN,
RESET, IRQ2, BR, MMAP, DR0, DR1, IS, IAL, IRD, IWR, IRQL0, IRQL1, IRQE, PWD.
14Output pins:
BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, IACK, PWDACK, A0–A13, DT0, DT1, CLKOUT, FL2-0.
15Although specified for TTL outputs, all ADSP-2183 outputs are CMOS-compatible and will drive to V
DD and GND, assuming no dc loads.
16Guaranteed but not tested.
17Three-statable pins: A0–A13, D0–D23,
PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, IAD0–IAD15, PF0–PF7.
180 V on
BR, CLKIN Active (to force three-state condition).
19Idle refers to ADSP-2183 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V
DD or GND.
10Current reflects device operating with no output loads.
11V
IN = 0.4 V and 2.4 V. For typical figures for supply currents, refer to Power Dissipation section.
12I
DD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are
1type 2 and type 6, and 20% are idle instructions.
13Applies to LQFP package type and Mini-BGA.
14Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
–12–
REV. C