C
參數(shù)資料
型號(hào)： ADSP-2183BSTZ-160
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/31頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 128LQFP
產(chǎn)品變化通告： Mold Change 11/Jul/2012
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 同步串行端口（SSP）
時(shí)鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 80kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
ADSP-2183
–25–
REV. C
CAPACITIVE LOADING
Figures 22 and 23 show the capacitive loading characteristics of
the ADSP-2183.
CL – pF
RISE
TIME
(0.4V
–
2.4V)
–
ns
0
160
20
40
60
80
100
120
140
25
20
15
10
5
T = +85 C
VDD = 3.0V
180
200
Figure 22. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
CL – pF
18
–2
0
200
40
80
120
160
16
10
6
2
NOMINAL
14
12
8
4
–4
–6
VALID
OUTPUT
DELAY
OR
HOLD
–
ns
Figure 23. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
put disable time (tDIS) is the difference of tMEASURED and tDECAY,
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
tDECAY, is dependent on the capacitive load, CL, and the current
load, iL, on the output pin. It can be approximated by the fol-
lowing equation:
t
DECAY =
C
L 0.5 V
i
L
from which
t
DIS = t MEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
1.5V
INPUT
OR
OUTPUT
1.5V
Figure 24. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
2.0V
1.0V
tENA
REFERENCE
SIGNAL
OUTPUT
tDECAY
VOH
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
tDIS
tMEASURED
VOL
(MEASURED)
VOH (MEASURED) – 0.5V
VOL (MEASURED) +0.5V
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
VOH
(MEASURED)
VOL
(MEASURED)
Figure 25. Output Enable/Disable
TO
OUTPUT
PIN
50pF
+1.5V
IOH
IOL
Figure 26. Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
TAMB = TCASE – (PD
× θCA)
TCASE = Case Temperature in
°C
PD = Power Dissipation in W
θCA = Thermal Resistance (Case-to-Ambient)
θJA = Thermal Resistance (Junction-to-Ambient)
θ
JC = Thermal Resistance (Junction-to-Case)
Package
JA
JC
CA
LQFP
50
°C/W
2
°C/W
48
°C/W
Mini-BGA
70.7
°C/W
7.4
°C/W
63.3
°C/W
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