參數(shù)資料
型號(hào): ADSP-2171BSZ-133
廠商: Analog Devices Inc
文件頁數(shù): 4/52頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 128PQFP
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類型: 定點(diǎn)
接口: 主機(jī)接口,串行端口
時(shí)鐘速率: 33MHz
非易失內(nèi)存: 外部
芯片上RAM: 10kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-MQFP(14x20)
包裝: 托盤
REV. A
–12–
ADSP-2171/ADSP-2172/ADSP-2173
Control Registers
ROM Enable/Data Memory Wait State
Control Register
0x3FFE
DWAIT4
DWAIT0
DWAIT1
DWAIT2
DWAIT3
ROM enable
1 = enable
0 = disable
1
01
11
1
15
14
13
12
11
10
9
876
5432
10
SPORT0 Control Register
0x3FF6
Multichannel Enable MCE
Internal Serial Clock Generation ISCLK
Receive Frame Sync Required RFSR
Receive Frame Sync Width RFSW
Multichannel Frame Delay MFD
Only If Multichannel Mode Enabled
Transmit Frame Sync Required TFSR
Transmit Frame Sync Width TFSW
SLEN Serial Word Length
DTYPE Data Format
00 = right justify, zero-fill unused MSBs
01 = right justify, sign extend into unused MSBs
10 = compand using
-law
11 = compand using A-law
INVRFS Invert Receive Frame Sync
INVTFS Invert Transmit Frame Sync
(or INVTDV Invert Transmit Data Valid
Only If Multichannel Mode Enabled)
IRFS Internal Receive Frame Sync Enable
0
00
0
15
14
13
12
11
10
9
8765
4321
0
ITFS Internal Transmit Frame Sync Enable
(or MCL Multichannel Length; 1 = 32 words, 0 = 24 words
Only If Multichannel Mode Enabled)
SPORT0 Multichannel Receive Word Enable Registers
1 = Channel Enabled
0 = Channel Ignored
SPORT0 Multichannel Transmit Word Enable Registers
1 = Channel Enabled
0 = Channel Ignored
0x3FF9
15 14 13 12 11 10
9
87654321
0
0x3FFA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0x3FF7
15 14 13 12 11 10
9876543
210
0x3FF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
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