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參數(shù)資料
| 型號： | ADSP-21489KSWZ-3A |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 100LQFP |
| 標(biāo)準包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | EBI/EMI，DAI，I²C，SPI，SPORT，UART/USART |
| 時鐘速率： | 350MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 5Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.10V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP-EP（14x14） |
| 包裝： | 托盤 |
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Rev. B
|
Page 16 of 68
|
March 2013
MLBCLK1
I
Media Local Bus Clock. This clock is generated by the MLB controller that is synchro-
nized to the MOST network and provides the timing for the entire MLB interface at
49.152 MHz at FS=48 kHz. When the MLB controller is not used, this pin should be
grounded.
MLBDAT1
I/O/T in 3
pin mode. I
in 5 pin
mode.
High-Z
Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device and
is received by all other MLB devices including the MLB controller. The MLBDAT line
carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB
controller is not used, this pin should be grounded.
MLBSIG1
I/O/T in 3
pin mode. I
in 5 pin
mode
High-Z
Media Local Bus Signal. This is a multiplexed signal which carries the Channel/Address
generated by the MLB Controller, as well as the Command and RxStatus bytes from
MLB devices. In 5-pin mode, this pin is input only. When the MLB controller is not used,
this pin should be grounded.
MLBDO1
O/T
High-Z
Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB mode.
This serves as the output data pin in 5-pin mode. When the MLB controller is not used,
this pin should be connected to ground.
MLBSO1
O/T
High-Z
Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB
mode. This serves as the output signal pin in 5-pin mode. When the MLB controller is
not used, this pin should be connected to ground.
TDI
I (ipu)
Test Data Input (JTAG). Provides serial data for the boundary scan logic.
TDO
O/T
High-Z
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS
I (ipu)
Test Mode Select (JTAG). Used to control the test state machine.
TCK
I
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the device.
TRST
I (ipu)
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the processor.
EMU
O (O/D, ipu)
High-Z
Emulation Status. Must be connected to the ADSP-2148x Analog Devices DSP Tools
product line of JTAG emulators target board connector only.
Table 11. Pin Descriptions (Continued)
Name
Type
State
During/
After Reset
Description
The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot
be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The
conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.
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| ADSP-21489KSWZ-3B | 功能描述:IC CCD SIGNAL PROCESSOR 176LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21489KSWZ-4A | 功能描述:IC CCD SIGNAL PROCESSOR 100LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21489KSWZ-4B | 功能描述:IC CCD SIGNAL PROCESSOR 176LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21489KSWZ-5B | 制造商:Analog Devices 功能描述:450 MHZ SHARC W/ STATIC VOLTAG 制造商:Analog Devices 功能描述:450 MHZ SHARC W/ STATIC VOLTAGE SCALING - Trays 制造商:Analog Devices 功能描述:Digital Signal Processors & Controllers - DSP, DSC High Perf 4th Generation 制造商:Analog Devices 功能描述:450 MHz SHARC w/ Static Voltage Scaling |
| ADSP-21489KSWZENGA | 制造商:Analog Devices 功能描述:SHARC PROCESSOR - Trays |
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