參數(shù)資料
型號(hào)： ADSP-21489KSWZ-3A
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 67/68頁(yè)
文件大小： 0K
描述： IC CCD SIGNAL PROCESSOR 100LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： EBI/EMI，DAI，I²C，SPI，SPORT，UART/USART
時(shí)鐘速率： 350MHz
非易失內(nèi)存： 外部
芯片上RAM： 5Mb
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.10V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 100-LQFP-EP（14x14）
包裝： 托盤(pán)
Rev. B
|
Page 8 of 68
|
March 2013
Arbitration logic to coordinate core and DMA transfers
between internal and external memory over the external
port.
Non-SDRAM external memory address space is shown in
External Port
The external port provides a high performance, glueless inter-
face to a wide variety of industry-standard memory devices. The
external port, available on the 176-lead LQFP, may be used to
interface to synchronous and/or asynchronous memory devices
through the use of its separate internal memory controllers. The
first is an SDRAM controller for connection of industry-stan-
dard synchronous DRAM devices while the second is an
asynchronous memory controller intended to interface to a
variety of memory devices. Four memory select pins enable up
to four separate devices to coexist, supporting any desired com-
bination of synchronous and asynchronous device types.
Asynchronous Memory Controller
The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with dif-
ferent timing parameters, enabling connection to a wide variety
of memory devices including SRAM, flash, and EPROM, as well
as I/O devices that interface with standard memory control
lines. Bank 0 occupies a 6M word window and banks 1, 2, and 3
occupy a 8M word window in the processor’s address space but,
if not fully populated, these windows are not made contiguous
by the memory controller logic.
SDRAM Controller
The SDRAM controller provides an interface of up to four sepa-
rate banks of industry-standard SDRAM devices at speeds up to
fSDCLK. Fully compliant with the SDRAM standard, each bank has
its own memory select line (MS0–MS3), and can be configured
to contain between 4M bytes and 256M bytes of memory.
SDRAM external memory address space is shown in Table 6.
NOTE: this feature is not available on the ADSP-21486 model.
A set of programmable timing parameters is available to config-
ure the SDRAM banks to support slower memory devices. Note
that 32-bit wide devices are not supported on the SDRAM and
AMI interfaces.
The SDRAM controller address, data, clock, and control pins
can drive loads up to distributed 30 pF. For larger memory sys-
tems, the SDRAM controller external buffer timing should be
selected and external buffering should be provided so that the
load on the SDRAM controller pins does not exceed 30 pF.
Note that the external memory bank addresses shown are for
normal-word (32-bit) accesses. If 48-bit instructions as well as
32-bit data are both placed in the same external memory bank,
care must be taken while mapping them to avoid overlap.
SIMD Access to External Memory
The SDRAM controller on the processor supports SIMD access
on the 64-bit EPD (external port data bus) which allows access
to the complementary registers on the PEy unit in the normal
word space (NW). This removes the need to explicitly access the
complimentary registers when the data is in external SDRAM
memory.
VISA and ISA Access to External Memory
The SDRAM controller on the ADSP-2148x processors sup-
ports VISA code operation which reduces the memory load
since the VISA instructions are compressed. Moreover, bus
fetching is reduced because, in the best case, one 48-bit fetch
contains three valid instructions. Code execution from the tra-
ditional ISA operation is also supported. Note that code
execution is only supported from bank 0 regardless of
VISA/ISA. Table 7 shows the address ranges for instruction
fetch in each mode.
Pulse-Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave-
forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non-
paired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
generating 16 PWM outputs in total. Each PWM group pro-
duces two pairs of PWM signals on the four PWM outputs.
Table 5. External Memory for Non-SDRAM Addresses
Bank
Size in
Words
Address Range
Bank 0
6M
0x0020 0000–0x007F FFFF
Bank 1
8M
0x0400 0000–0x047F FFFF
Bank 2
8M
0x0800 0000–0x087F FFFF
Bank 3
8M
0x0C00 0000–0x0C7F FFFF
Table 6. External Memory for SDRAM Addresses
Bank
Size in
Words
Address Range
Bank 0
62M
0x0020 0000–0x03FF FFFF
Bank 1
64M
0x0400 0000–0x07FF FFFF
Bank 2
64M
0x0800 0000–0x0BFF FFFF
Bank 3
64M
0x0C00 0000–0x0FFF FFFF
Table 7. External Bank 0 Instruction Fetch
Access Type
Size in
Words
Address Range
ISA (NW)
4M
0x0020 0000–0x005F FFFF
VISA (SW)
10M
0x0060 0000–0x00FF FFFF
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