參數(shù)資料
型號(hào)： ADSP-21478BBCZ-2A
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 58/76頁(yè)
文件大?。?/td> 0K
描述： IC DSP SHARK 266MHZ 196CSPBGA
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART
時(shí)鐘速率： 266MHz
非易失內(nèi)存： ROM（4Mb）
芯片上RAM： 3Mb
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 196-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 196-CSPBGA（12x12）
包裝： 托盤
Rev. C
|
Page 61 of 76
|
July 2013
Shift Register
Table 54. Shift Register
Parameter
Min
Max
Unit
Timing Requirements
tSSDI
SR_SDI Setup Before SR_SCLK Rising Edge
7
ns
tHSDI
SR_SDI Hold After SR_SCLK Rising Edge
2
ns
tSSDIDAI
1
DAI_P08–01 (SR_SDI) Setup Before DAI_P08–01 (SR_SCLK) Rising Edge
7
ns
tHSDIDAI
DAI_P08–01 (SR_SDI) Hold After DAI_P08–01 (SR_SCLK) Rising Edge
2
ns
tSSCK2LCK
2
SR_SCLK to SR_LAT Setup
2
ns
tSSCK2LCKDAI
DAI_P08–01 (SR_SCLK) to DAI_P08–01 (SR_LAT) Setup
2
ns
tCLRREM2SCK
Removal Time SR_CLR to SR_SCLK
3 × tPCLK – 5
ns
tCLRREM2LCK
Removal Time SR_CLR to SR_LAT
2 × tPCLK – 5
ns
tCLRW
SR_CLR Pulse Width
4 × tPCLK – 5
ns
tSCKW
SR_SCLK Clock Pulse Width
2 × tPCLK – 2
ns
tLCKW
SR_LAT Clock Pulse Width
2 × tPCLK – 5
ns
fMAX
Maximum Clock Frequency SR_SCLK or SR_LAT
fPCLK 4MHz
Switching Characteristics
ns
tDSDO1
3
SR_SDO Hold After SR_SCLK Rising Edge
3
ns
tDSDO2
SR_SDO Max. Delay After SR_SCLK Rising Edge
13
ns
tDSDODAI1
SR_SDO Hold After DAI_P08–01 (SR_SCLK) Rising Edge
3
ns
tDSDODAI2
SR_SDO Max. Delay After DAI_P08–01 (SR_SCLK) Rising Edge
13
ns
tDSDOSP1
SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge
–2
ns
tDSDOSP2
SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge
5
ns
tDSDOPCG1
3, 5, 6
SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge
–2
ns
tDSDOPCG2
SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge
5
ns
tDSDOCLR1
SR_CLR to SR_SDO Min. Delay
4
ns
tDSDOCLR2
SR_CLR to SR_SDO Max. Delay
13
ns
tDLDO1
SR_LDO Hold After SR_LAT Rising Edge
3
ns
tDLDO2
SR_LDO Max. Delay After SR_LAT Rising Edge
13
ns
tDLDODAI1
SR_LDO Hold After DAI_P08–01 (SR_LAT) Rising Edge
3
ns
tDLDODAI2
SR_LDO Max. Delay After DAI_P08–01 (SR_LAT) Rising Edge
13
ns
tDLDOSP1
SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge
–2
ns
tDLDOSP2
SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge
5
ns
tDLDOPCG1
SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge
–2
ns
tDLDOPCG2
SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge
5
ns
tDLDOCLR1
SR_CLR to SR_LDO Min. Delay
4
ns
tDLDOCLR2
SR_CLR to SR_LDO Max. Delay
14
ns
1 Any of the DAI_P08–01 pins can be routed to the shift register clock, latch clock and serial data input via the SRU.
2 Both clocks can be connected to the same clock source. If both clocks are connected to same clock source, then data in the 18-stage shift register is always one cycle ahead of
latch register data.
3 For setup/hold timing requirements of off-chip shift register interfacing devices.
4 SPORTx serial clock out, frame sync out, and serial data outputs are routed to shift register block internally and are also routed onto DAI_P20–01.
5 PCG serial clock output is routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SR_LAT and SDI internally.
6 PCG Serial clock and frame sync outputs are routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SDI internally.
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