參數(shù)資料
型號(hào)： ADSP-21478BBCZ-2A
廠商： Analog Devices Inc
文件頁數(shù)： 10/76頁
文件大?。?/td> 0K
描述： IC DSP SHARK 266MHZ 196CSPBGA
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART
時(shí)鐘速率： 266MHz
非易失內(nèi)存： ROM（4Mb）
芯片上RAM： 3Mb
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 196-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 196-CSPBGA（12x12）
包裝： 托盤
Rev. C
|
Page 18 of 76
|
July 2013
THD_P
I
Thermal Diode Anode. When not used, this pin can be left floating.
THD_M
O
Thermal Diode Cathode. When not used, this pin can be left floating.
MLBCLK
I
Media Local Bus Clock. This clock is generated by the MLB controller that is
synchronized to the MOST network and provides the timing for the entire MLB
interface at 49.152 MHz at FS = 48 kHz. When the MLB controller is not used, this
pin should be grounded.
MLBDAT
I/O/T in 3 pin
mode.
I in 5 pin mode.
High-Z
Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device
and is received by all other MLB devices including the MLB controller. The
MLBDAT line carries the actual data. In 5-pin MLB mode, this pin is an input only.
When the MLB controller is not used, this pin should be grounded.
MLBSIG
I/O/T in 3 pin
mode.
I in 5 pin mode
High-Z
Media Local Bus Signal. This is a multiplexed signal which carries the
Channel/Address generated by the MLB Controller, as well as the Command and
RxStatus bytes from MLB devices. In 5-pin mode, this pin is input only. When the
MLB controller is not used, this pin should be grounded.
MLBDO
O/T
High-Z
Media Local Bus Data Output (in 5 Pin Mode). This pin is used only in 5-pin MLB
mode and serves as the output data pin. When the MLB controller is not used, this
pin should be grounded.
MLBSO
O/T
High-Z
Media Local Bus Signal Output (in 5 Pin Mode). This pin is used only in 5-pin
MLB mode and serves as the output signal pin. When the MLB controller is not
used, this pin should be grounded.
SR_SCLK
I (ipu)
Shift Register Serial Clock. (Active high, rising edge sensitive)
SR_CLR
I (ipu)
Shift Register Reset. (Active low)
SR_SDI
I (ipu)
Shift Register Serial Data Input.
SR_SDO
O (ipu)
Driven Low
Shift Register Serial Data Output.
SR_LAT
I (ipu)
Shift Register Latch Clock Input. (Active high, rising edge sensitive)
SR_LDO17–0
O/T (ipu)
High-Z
Shift Register Parallel Data Output.
RTXI
I
RTC Crystal Input. If RTC is not used, then this pin needs to be NC (no connect)
and the RTC_PDN and RTC_BUSDIS bits of RTC_INIT register must be set to 1.
RTXO
O
RTC Crystal Output. If RTC is not used, then this pin needs to be NC (No Connect).
RTCLKOUT
O (ipd)
RTC Clock Output. For calibration purposes. The clock runs at 1 Hz. If RTC is not
used, then this pin needs to be NC (No Connect).
Table 11. Pin Descriptions (Continued)
Name
Type
State During/
After Reset
Description
The following symbols appear in the Type column of Table 11: A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors
cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The
range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions
the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.
Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on
Page 70.
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