參數(shù)資料
型號(hào)： ADSP-2141LKS-E1
廠商： ANALOG DEVICES INC
元件分類： 加密電路
英文描述： DSP
中文描述： TELECOM, DATA ENCRYPTION CIRCUIT, PQFP208
封裝： METRIC, PLASTIC, QFP-208
文件頁(yè)數(shù)： 18/39頁(yè)
文件大?。?/td> 257K
代理商： ADSP-2141LKS-E1
REV. 0
ADSP-2141L
–18–
DC SPECIFICATIONS– PCI Bus Pins
K Grade
Parameter
Test Conditions
Min
Max
Unit
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OZH
I
OZL
C
I
C
CLK
C
IDSEL
L
PIN
Hi-Level Input Voltage
1, 2
Lo-Level Input Voltage
1, 2
Hi-Level Output Voltage
1, 3
Lo-Level Output Voltage
1, 3
Hi-Level Input Current
2
Lo-Level Input Current
2
Three-State Leakage Current
4
Three-State Leakage Current
1
Input Pin Capacitance
PCI CLK Pin Capacitance
PCI IDSEL Pin Capacitance
5
Pin Inductance
0.5 V
DD
–0.5
0.9 V
DD
V
DD
+ 0.5
0.3 V
DD
V
V
V
V
μ
A
μ
A
μ
A
μ
A
pF
pF
pF
nH
I
OUT
= –500
μ
A
I
OUT
= 1500
μ
A
0 < V
IN
< V
DD
0 < V
IN
< V
DD
0 < V
IN
< V
DD
0 < V
IN
< V
DD
T
AMB
= 25
°
C
T
AMB
= 25
°
C
T
AMB
= 25
°
C
0.1 V
DD
10
10
10
10
10
12
8
20
5
NOTES
1
Bidirectional pins: MPLX_BUS [31:0}, MPLX1–4, MPLX7–10, MPLX12
2
Input only pins: MPLX_RESET, MPLX5, MPLX6, PCI_CLK, PCI_PAR, PCI_IRDY, PCI_STOP
3
Output only pins: MPLX11
4
Leakage currents include High-Z output leakage for bidirectional buffers with three-state outputs.
5
Lower capacitance of IDSEL (MPLX_5) input-only pin allows for nonresistive connection to Address/Data bus.
TIMING PARAMETERS
PCI Clock
(Guaranteed Over Operating Temperature and Digital Supply Range)
The ADSP-2141L is targeted for use in PCI add-on I/O slave card designs. It provides a glueless interface to the PCI bus. All bus
drivers are compliant with PCI interface electrical switching and drive capability specifications.
The ADSP-2141L does not implement the following signals:
LOCK
,
INTB
,
INTC
,
INTD
,
SBO
,
SDONE
,
CLKRUN,
AD[64:32],
C/BE
[7:4],
REQ
64,
ACK
64, PAR64.
Parameter
Min
Max
Unit
Timing Requirements:
t
CYC
t
HIGH
t
LOW
CLK Cycle Time
CLK High Time
CLK Low Time
CLK Slew Rate
1
RST
Slew Rate
2
25
11
11
1
50
100
ns
ns
ns
V/ns
mV/ns
4
NOTES
1
Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the waveform as
shown in Figure 8.
2
The minimum
RST
slew rate applies only to the rising (deassertion) edge of the reset signal, and ensures that system noise cannot render an otherwise monotonic
signal to appear to bounce in the switching range.
0.2V
CC
2V p-p
(
MINIMUM
)
0.3V
CC
0.4V
CC
0.5V
CC
0.6V
CC
t
LOW
t
HIGH
t
CYC
Figure 8. Clock Waveform
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-2141LKS-N1 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:Digital Signal Processor, 16 Bit, 208 Pin, Plastic, QFP
ADSP-2141LKSZ-N1 制造商:Analog Devices 功能描述:
ADSP2142MKS300X 制造商:AD 功能描述:*
ADSP-21462W 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor material that is subject to change without notice
ADSP-21465W 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor material that is subject to change without notice
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