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參數(shù)資料
| 型號： | ADSP-2141L |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 加密電路 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP208 |
| 封裝： | METRIC, PLASTIC, QFP-208 |
| 文件頁數(shù)： | 33/39頁 |
| 文件大?。?/td> | 257K |
| 代理商： | ADSP-2141L |
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REV. 0
ADSP-2141L
–33–
CAPACITIVE LOADING
Figures 23 and 24 show the capacitive loading characteristics of
the ADSP-2141L.
C
L
– pF
R
0
50
18
14
T = +70
8
C
V
DD
= 3.0V
16
12
10
8
6
4
2
0
100
150
200
250
300
Figure 23. Typical Output Rise Time vs. Load Capacitance,
C
L
(at Maximum Ambient Operating Temperature)
C
L
– pF
18
–2
0
250
50
100
150
200
16
10
6
2
NOMINAL
14
12
8
4
–4
V
O
Figure 24. Typical Output Valid Delay or Hold vs. Load
Capacitance, C
L
(at Maximum Ambient Operating
Temperature)
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
put disable time (t
DIS
) is the difference of t
MEASURED
and t
DECAY
,
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
t
DECAY
, is dependent on the capacitive load, C
L
, and the current
load,
i
L
, on the output pin. It can be approximated by the fol-
lowing equation:
t
DECAY
=
C
L
0.5
V
i
L
from which
t
DIS
=
t
MEASURED
–
t
DECAY
is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.
1.5V
INPUT
OR
OUTPUT
1.5V
Figure 25. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t
ENA
) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
2.0V
1.0V
t
ENA
REFERENCE
SIGNAL
OUTPUT
t
DECAY
V
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
t
DIS
t
MEASURED
V
(MEASURED)
V
OH
(MEASURED) – 0.5V
V
OL
(MEASURED) +0.5V
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
V
(MEASURED)
V
(MEASURED)
Figure 26. Output Enable/Disable
TO
OUTPUT
PIN
50pF
+1.5V
I
OH
I
OL
Figure 27. Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-2141LKS-E1 | 制造商:Analog Devices 功能描述:TELECOM, DATA ENCRYPTION CIRCUIT, PQFP208 |
| ADSP-2141LKS-N1 | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:Digital Signal Processor, 16 Bit, 208 Pin, Plastic, QFP |
| ADSP-2141LKSZ-N1 | 制造商:Analog Devices 功能描述: |
| ADSP2142MKS300X | 制造商:AD 功能描述:* |
| ADSP-21462W | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor material that is subject to change without notice |
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