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參數(shù)資料
| 型號： | ADSP-21368KBPZ-3A |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 47/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 32BIT 400MHZ 256BGA |
| 產(chǎn)品培訓(xùn)模塊： | SHARC Processor Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | DAI，DPI |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | ROM（768 kB） |
| 芯片上RAM： | 256kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.30V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 托盤 |
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Rev. F
|
Page 51 of 64
|
October 2013
OUTPUT DRIVE CURRENTS
Figure 39 shows typical I-V characteristics for the output driv-
ers and Figure 40 shows typical I-V characteristics for the
SDCLK output drivers. The curves represent the current drive
capability of the output drivers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 14 on Page 23 through Table 42 on Page 50. These include
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 41.
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 41. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 42). Figure 47 and
Figure 48 show graphically how output delays and holds vary
with load capacitance. The graphs of Figure 43 through
Figure 48 may not be linear outside the ranges shown for Typi-
cal Output Delay vs. Load Capacitance and Typical Output Rise
Time (20% to 80%, V = Min) vs. Load Capacitance.
Figure 39. Typical Drive at Junction Temperature
Figure 40. SDCLK1–0 Drive at Junction Temperature
SWEEP (VDDEXT) VOLTAGE (V)
-
20
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
0
-
40
-
30
20
40
-
10
S
O
U
R
C
E
(V
D
E
X
T
)
C
U
R
E
N
T
(m
A
)
VOL
3.11V, 125°C
3.3V, 25°C
3.47V, -45°C
VOH
30
10
3.11V, 125°C
3.3V, 25°C
3.47V, -45°C
3.11V, 105°C
-
60
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
0
-
45
-
30
60
75
-
15
S
O
U
R
C
E
(V
D
E
X
T
)
C
U
R
E
N
T
(m
A
)
VOL
3 .1 3 V, 12 5 °C
3.3 V, 25 °C
3 .47 V, -45 °C
V
OH
3.1 3V, 1 05 °C
45
-
90
-
75
-
105
30
15
3.1 3V, 1 25 °C
3.3 V, 2 5°C
3 .47 V, -45°C
3 .1 3 V, 10 5° C
S WEE P (VDDEXT)VOLTAG E (V)
Figure 41. Voltage Reference Levels for AC Measurements
Figure 42. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
INPUT
OR
OUTPUT
1.5V
T1
ZO = 50
Ω (impedance)
TD = 4.04
± 1.18 ns
2pF
TESTER PIN ELECTRONICS
50
Ω
0.5pF
70
Ω
400
Ω
45
Ω
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
1.5V
DUT
OUTPUT
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