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參數(shù)資料
| 型號(hào)： | ADSP-21267SKSTZ-X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Preliminary Technical Data |
| 中文描述： | 16-BIT, 50 MHz, OTHER DSP, PQFP144 |
| 封裝： | MS-026BFB, LQFP-144 |
| 文件頁數(shù)： | 7/44頁 |
| 文件大?。?/td> | 454K |
| 代理商： | ADSP-21267SKSTZ-X |
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ADSP-21267
Rev. PrA
|
Page 7 of 44
|
January 2004
PRELIMINARY TECHNICAL DATA
slave device. The ADSP-21267 SPI-compatible peripheral
implementation also features programmable baud rates up to
37.5 MHz, clock phases, and polarities. The ADSP-21267 SPI-
compatible port uses open drain drivers to support a multi-mas-
ter configuration and to avoid data contention.
Parallel Port
The Parallel Port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15-0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16-
bit, the maximum data transfer rate is one-third the core clock
speed. As an example, for a clock rate of 150 MHz, this is equiv-
alent to 50 Mbytes/sec.
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral-
lel port register read/write functions. The RD, WR, and ALE
(Address Latch Enable) pins are the control pins for the parallel
port.
Timers
The ADSP-21267 has a total of four timers: a core timer able to
generate periodic software interrupts and three general purpose
timers that can that can generate periodic interrupts and be
independently set to operate in one of three modes:
Pulse Waveform Generation mode
Pulse Width Count/Capture mode
External Event Watchdog mode
The core timer can be configured to use FLAG3 as a Timer
Expired output signal, and each general purpose timer has one
bidirectional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables all three
general purpose timers independently.
ROM Based Security
The ADSP-21267 has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the DSP does not boot-load any exter-
nal code, executing exclusively from internal SRAM/ROM.
Additionally, the DSP is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or Test Access Port, will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.
Program Booting
The internal memory of the ADSP-21267 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG1-0) pins. Selection of
the boot source is controlled via the SPI as either a master or
slave device, or it can immediately begin executing from ROM.
Phased Locked Loop
The ADSP-21267 uses an on-chip Phase Locked Loop (PLL) to
generate the internal clock for the core. On power up, the
CLKCFG1-0 pins are used to select ratios of 16:1, 8:1, and 3:1.
After booting, numerous other ratios can be selected via soft-
ware control. The ratios are made up of software configurable
numerator values from 1 to 32 and software configurable divi-
sor values of 1, 2, 4, 8, and 16.
Power Supplies
The ADSP-21267 has separate power supply connections for the
internal (V
DDINT
), external (V
DDEXT
), and analog (A
VDD
/A
VSS
)
power supplies. The internal and analog supplies must meet the
1.2 V requirement. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the
same power supply.
Note that the analog supply (A
VDD
) powers the ADSP-21267’s
clock generator PLL. To produce a stable clock, you should pro-
vide an external circuit to filter the power input to the A
VDD
pin.
Place the filter as close as possible to the pin. For an example cir-
cuit, see
Figure 4
. To prevent noise coupling, use a wide trace
for the analog ground (A
VSS
) signal and install a decoupling
capacitor as close as possible to the pin. Note that the A
VSS
and
A
VDD
pins specified in
Figure 4
are inputs to the SHARC and not
the analog ground plane on the board.
TARGET BOARD JTAG EMULATOR CONNECTOR
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21267 pro-
cessor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor's JTAG interface ensures that the
emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate emulator hardware user's guide.
DEVELOPMENT TOOLS
The ADSP-21267 is supported by a complete automotive refer-
ence design and development board as well as by a complete
home audio reference design board available from Analog
Devices. These boards implement complete audio decoding and
post processing algorithms that are factory programmed into
Figure 4. Analog Power (A
VDD
) Filter Circuit
V
DDINT
A
VDD
A
VSS
0.01 F
0.1 F
10
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| adsp-21362bbc-1aa | 制造商:Analog Devices 功能描述: |
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