參數(shù)資料
型號: ADSP-21267SKSTZ-X
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: Preliminary Technical Data
中文描述: 16-BIT, 50 MHz, OTHER DSP, PQFP144
封裝: MS-026BFB, LQFP-144
文件頁數(shù): 36/44頁
文件大小: 454K
代理商: ADSP-21267SKSTZ-X
Rev. PrA
|
Page 36 of 44
|
January 2004
ADSP-21267
PRELIMINARY TECHNICAL DATA
OUTPUT DRIVE CURRENTS
Figure 28
shows typical I-V characteristics for the output driv-
ers of the ADSP-21267. The curves represent the current drive
capability of the output drivers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear
Table 9
on page 18
through
Table 30 on page 35
. These include output
disable time, output enable time, and capacitive loading.
Timing is measured on signals when they cross the 1.5 V level as
described in
Figure 30 on page 36
. All delays (in nanoseconds)
are measured between the point that the first signal reaches
1.5 V and the point that the second signal reaches 1.5 V.
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
12 pF on all pins (see
Figure 29
).
Figure 32
shows graphically
how output delays and holds vary with load capacitance (Note
that this graph or derating does not apply to output disable
delays. The graphs of
Figure 31
,
Figure 32
and
Figure 33
may
not be linear outside the ranges shown for Typical Output Delay
vs. Load Capacitance and Typical Output Rise Time (20%-80%,
V=Min) vs. Load Capacitance.
Figure 28. ADSP-21267 Typical Drive
Figure 29. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 30. Voltage Reference Levels for AC Measurements
SWEEP (VDDEXT) VOLTAGE - V
-20
0
3.5
0.5
1
1.5
2
2.5
3
0
-40
-30
20
40
-10
S
VOL TBD
VOH TBD
30
10
1.5V
30pF
TO
OUTPUT
PIN
50
INPUT
OOR
1.5V
Figure 31. Typical Output Rise Time
(20%-80%, V
DDEXT
= Max)
Figure 32. Typical Output Rise/Fall Time
(20%-80%, V
DDEXT
= Min)
LOAD CAPACITANCE - PF
8.0
0
0
120
40
100
12.0
4.0
2.0
10.0
6.0
R
80
60
20
TBD
LOAD CAPACITANCE - pF
12
0
120
20
40
60
80
100
10
8
6
4
R
2
0
TBD
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