參數(shù)資料
型號(hào)： ADSP-21262SKBC-200
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 66.67 MHz, OTHER DSP, PBGA136
封裝： MO-205AE, BGA-136
文件頁數(shù)： 18/44頁
文件大小： 1295K
代理商： ADSP-21262SKBC-200
Rev. A
|
Page 18 of 44
|
May 2004
ADSP-21262
Power-Up Sequencing
The timing requirements for DSP startup are given in
Table 9
.
Table 9. Power-Up Sequencing Timing Requirements (DSP Startup)
Parameter
Min
Max
Unit
Timing Requirements
t
RSTVDD
t
IVDDEVDD
t
CLKVDD
t
CLKRST
t
PLLRST
RESET Low Before V
DDINT
/V
DDEXT
on
V
DDINT
on Before V
DDEXT
CLKIN Valid After V
DDINT
/V
DDEXT
valid
1
CLKIN Valid Before RESET Deasserted
0
ns
–50
200
ms
0
10
2
20
3
200
ms
μs
PLL Control Setup Before RESET Deasserted
μs
Switching Characteristic
t
CORERST
DSP Core Reset Deasserted After RESET Deasserted
4096t
CK4,
5
1
Valid V
/V
assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for startup time.
Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles.
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on t
SRST
specification in
Table 11
. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
Figure 6. Power-Up Sequencing
CLKIN
RESET
t
RSTVDD
RSTOUT*
VDDEXT
VDDINT
t
PLLRST
t
CLKRST
t
CLKVDD
t
IVDDEVDD
CLK_CFG1-0
t
CO RERST
*MULTIPLEXED WITH CLKOUT
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