參數(shù)資料
型號(hào): ADSP-21062KS-133
廠商: Analog Devices Inc
文件頁數(shù): 22/64頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 32BIT 240MQFP
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: 主機(jī)接口,連接端口,串行端口
時(shí)鐘速率: 33MHz
非易失內(nèi)存: 外部
芯片上RAM: 256kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 240-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 240-MQFP-EP(32x32)
包裝: 托盤
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Rev. F
|
Page 29 of 64
|
March 2008
Synchronous Read/Write—Bus Slave
Use these specifications for bus master accesses of a slave’s IOP
registers or internal memory (in multiprocessor memory space).
The bus master must meet the bus slave timing requirements.
Table 17. Synchronous Read/Write—Bus Slave
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tSADRI
Address, SW Setup Before CLKIN
15 + DT/2
ns
tHADRI
Address, SW Hold After CLKIN
5 + DT/2
ns
tSRWLI
RD/WR Low Setup Before CLKIN1
9.5 + 5DT/16
ns
tHRWLI
RD/WR Low Hold After CLKIN2
–4 – 5DT/16
8 + 7DT/16
ns
tRWHPI
RD/WR Pulse High
3
ns
tSDATWH
Data Setup Before WR High
5
ns
tHDATWH
Data Hold After WR High
1
ns
Switching Characteristics
tSDDATO
Data Delay After CLKIN3
18 + 5DT/16
ns
tDATTR
Data Disable After CLKIN4
0 – DT/8
7 – DT/8
ns
tDACKAD
ACK Delay After Address, SW5
9ns
tACKTR
ACK Disable After CLKIN5
–1 – DT/8
6 – DT/8
ns
1 t
SRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, tSRWLI (min)= 4 + DT/8.
2 For ADSP-21060C specification is –3.5 – 5DT/16 ns min, 8 + 7DT/16 ns max; for ADSP-21060LC specification is –3.75 – 5DT/16 ns min, 8 + 7DT/16 ns max.
3 For ADSP-21062/ADSP-21062L/ADSP-21060C specification is 19 + 5DT/16 ns max; for ADSP-21060LC specification is 19.25 + 5DT/16 ns max.
4 See Example System Hold Time Calculation on Page 47 for calculation of hold times given capacitive and dc loads.
5 t
DACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and inputs have setup times
greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of the state
of MMSWS or strobes. A slave will three-state ACK every cycle with tACKTR.
Figure 17. Synchronous Read/Write—Bus Slave
CLKIN
ADDRESS
ACK
RD
DATA
(OU T)
WR
WRITE ACCESS
DATA
(IN)
READ ACCESS
tSADRI
tHADRI
tDACKAD
tACKTR
tHRWLI
tSRWLI
tSDDATO
tDATTR
tSRWLI
tHRWLI
tHDATWH
tSDATWH
tRWH PI
tRWHPI
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