參數(shù)資料
型號： ADSP-21020
廠商： Analog Devices, Inc.
元件分類： 數(shù)字信號處理
英文描述： 32/40-Bit IEEE Floating-Point DSP Microprocessor(浮點(diǎn)型DSP處理器)
中文描述： 32/40 IEEE浮點(diǎn)DSP微處理器（浮點(diǎn)型DSP的處理器）
文件頁數(shù)： 25/32頁
文件大?。?/td> 424K
代理商： ADSP-21020
ADSP-21020
REV. C
–25–
Capacitive Loading
Output delays are based on standard capacitive loads: 100 pF
on address, select, page and strobe pins, and 50 pF on all others
(see Figure 14). For different loads, these timing parameters
should be derated. See the Hardware Configuration chapter of
the
ADSP-21020 User’s Manual
for further information on
derating of timing specifications.
Figures 16 and 17 show how the output rise time varies with
capacitance. Figures 18 and 19 show how output delays vary
with capacitance. Note that the graphs may not be linear outside
the ranges shown.
10
0
200
3
1
50
2
25
6
4
5
7
8
9
175
150
125
100
75
LOAD CAPACITANCE – pF
R
1
2
9.18
1.46
1.31
NOTES:
(1) OUTPUT PINS BG, TIMEXP
(2) OUTPUT PINS PMD47–0, DMD39–0, FLAG3–0
3.95
Figure 16. Typical Output Rise Time vs. Load
Capacitance (at Maximum Case Temperature)
0
200
3
1
50
2
25
4
175
125
100
75
150
LOAD CAPACITANCE – pF
R
1
2
3.59
3.00
1.33
0.85
NOTES:
(1) OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0, DMS3–0, DMPAGE, TDO
(2) OUTPUT PINS PMRD, PMWR, DMRD, DMWR
π
Figure 17. Typical Output Rise Time vs. Load
Capacitance (at Maximum Case Temperature)
10
–2
200
4
NOMINAL
50
2
25
8
6
175
125
100
75
150
1
2
11.19
5.34
–1.86
– 0.89
LOAD CAPACITANCE – pF
O
NOTES:
(1) OUTPUT PINS BG, TIMEXP
(2) OUTPUT PINS PMD47–0, DMD39–0, FLAG3–0
12
Figure 18. Typical Output Delay or Hold vs. Load
Capacitance (at Maximum Case Temperature)
–3
200
NOMINAL
–2
50
–1
25
3
1
2
175
150
125
100
75
1
2
2.99
2.27
– 1.70
– 2.24
LOAD CAPACITANCE – pF
O
NOTES:
(1) OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0, DMS3–0, DMPAGE, TDO
(2) OUTPUT PINS PMRD, PMWR, DMRD, DMWR
Figure 19. Typical Output Delay or Hold vs. Load
Capacitance (at Maximum Case Temperature)
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