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參數(shù)資料
| 型號： | ADSP-21020 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32/40-Bit IEEE Floating-Point DSP Microprocessor(浮點型DSP處理器) |
| 中文描述： | 32/40 IEEE浮點DSP微處理器（浮點型DSP的處理器） |
| 文件頁數(shù)： | 13/32頁 |
| 文件大?。?/td> | 424K |
| 代理商： | ADSP-21020 |
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ADSP-21020
REV. C
–13–
TIMING PARAMETERS
General Notes
See Figure 15 on page 24 for voltage reference levels. Use the exact timing information given. Do not attempt to derive parameters
from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the
values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add parameters to
derive other specifications.
Clock Signal
K/B/T Grade
20 MHz
Min
K/B/T Grade
25 MHz
Min
B/T Grade
30 MHz
Min
K Grade
33.3 MHz
Min
Parameter
Max
Max
Max
Max
Unit
Timing Requirement:
t
CK
t
CKH
t
CKL
CLKIN Period
CLKIN Width High
CLKIN Width Low
50
10
10
150
40
10
10
150
33
10
10
150
30
10
10
150
ns
ns
ns
CLKIN
t
CKH
t
CKL
t
CK
Figure 3. Clock
Reset
K/B/T Grade K/B/T Grade
B/T Grade
K Grade
20 MHz
Min
25 MHz
Min
30 MHz
Min Max
33.3 MHz
Min Max
Frequency Dependency*
Min
Parameter
Max
Max
Max
Unit
Timing Requirement:
t
WRST1
RESET Width Low
t
SRST2
RESET Setup before CLKIN High 29
200
160
24
132
21
120
19
4t
CK
29 + DT/2
ns
ns
50
40
33
30
30
NOTES
DT = t
CK
–50 ns
1
Applies after the power-up sequence is complete. At power up, the Internal Phase Locked Loop requires no more than 1000 CLKIN cycles while RESET is low,
assuming stable V
DD
and CLKIN (not including clock oscillator start-up time).
2
Specification only applies in cases where multiple ADSP-21020 processors are required to execute in program counter lock-step (all processors start execution at
location 8 in the same cycle). See the Hardware Configuration chapter of the
ADSP-21020 User’s Manual
for reset sequence information.
CLKIN
t
WRST
t
SRST
RESET
Figure 4. Reset
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21060LC | DSP Microcomputer(DSP 微計算機) |
| ADSP-21060C | DSP Microcomputer(DSP 微計算機) |
| ADSP-21261 | SHARC Embedded Processor |
| ADSP-21261SKBC-150 | SHARC Embedded Processor |
| ADSP-21261SKBCZ150 | SHARC Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21020BG-100 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32/40-Bit IEEE Floating-Point DSP Microprocessor |
| ADSP-21020BG-120 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32/40-Bit IEEE Floating-Point DSP Microprocessor |
| ADSP-21020BG-80 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32/40-Bit IEEE Floating-Point DSP Microprocessor |
| ADSP-21020KG-100 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32/40-Bit IEEE Floating-Point DSP Microprocessor |
| ADSP-21020KG-133 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32/40-Bit IEEE Floating-Point DSP Microprocessor |
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