參數(shù)資料
型號(hào): ADSP-21020
廠商: Analog Devices, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: 32/40-Bit IEEE Floating-Point DSP Microprocessor(浮點(diǎn)型DSP處理器)
中文描述: 32/40 IEEE浮點(diǎn)DSP微處理器(浮點(diǎn)型DSP的處理器)
文件頁數(shù): 16/32頁
文件大小: 424K
代理商: ADSP-21020
ADSP-21020
REV. C
–16–
Bus Request/Bus Grant
K/B/T Grade K/B/T Grade B/T Grade
K Grade
20 MHz
Min
25 MHz
Min
30 MHz
33.3 MHz
Min Max
Frequency Dependency*
Min
Max
Parameter
Max
Max Min Max
Unit
Timing Requirement:
t
HBR
BR
Hold after CLKIN High
t
SBR
BR
Setup before CLKIN High
0
18
0
15
0
13
0
12
ns
ns
18 + 5DT/16
Switching Characteristic:
t
DMDBGL
Memory Interface Disable to
BG
Low –2
t
DME
CLKIN High to Memory Interface
Enable
t
DBGL
CLKIN High to
BG
Low
t
DBGH
CLKIN High to
BG
High
–2
–2
–2
ns
25
20
16
15
25 + DT/2
ns
ns
ns
22
22
22
22
22
22
22
22
NOTES
*DT = t
CK
– 50 ns.
Memory Interface = PMA23-0, PMD47-0,
PMS1-0
,
PMRD
,
PMWR
, PMPAGE, DMA31-0, DMD39-0,
DMS3-0
,
DMRD
,
DMWR
, DMPAGE.
Buses are not granted until completion of current memory access.
See the Memory Interface chapter of the
ADSP-21020 User’s Manual
for
BG
,
BR
cycle relationships.
CLKIN
t
HBR
MEMORY
INTERFACE
t
SBR
t
DBGL
t
DMDBGL
t
HBR
t
SBR
t
DME
t
DBGH
BR
BG
Figure 8. Bus Request/Bus Grant
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