參數(shù)資料
型號： ADS8507I
英文描述： 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
中文描述： 16位40 kSPS的低功耗采樣模擬到數(shù)字轉換的內(nèi)部基準，并行/串行接口
文件頁數(shù)： 15/32頁
文件大小： 738K
代理商： ADS8507I
www.ti.com
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
21
t
9
t
21
t
9
Hi-Z State
High Byte
Hi-Z State
Low Byte
Hi-Z State
t
4
t
3
t
1
R/C
BUSY
CS
Data Bus
BYTE
PARALLEL OUTPUT (During a Conversion)
After conversion
N
has been initiated, valid data from conversion
N–1
can be read and is valid up to 12 μs after
the start of conversion
N
. Do not attempt to read data beyond 12 μs after the start of conversion
N
until BUSY
(pin 24) goes high; this may result in reading invalid data. Refer to
Table 5
and
Figure 33
and
Figure 34
for
timing constraints.
ADS8507
SLAS381–DECEMBER 2006
Figure 34. CS to Control Conversion and Read Timing With Parallel Outputs
Table 5. Conversion and Data Timing, T
A
= -40°C to 85°C
SYMBOL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
DESCRIPTION
MIN
0.04
TYP
MAX
12
20
85
20
UNITS
μs
μs
ns
μs
ns
ns
μs
ns
ns
ns
μs
ns
μs
μs
ns
ns
ns
ns
ns
ns
Convert pulse width
Data valid delay after R/C low
BUSY delay from start of conversion
BUSY Low
BUSY delay after end of conversion
Aperture delay
Conversion time
Acquisition time
Bus relinquish time
BUSY delay after data valid
Previous data valid after start of conversion
Bus access time and BYTE delay
Start of conversion to DATACLK delay
DATACLK period
Data valid to DATACLK high delay
Data valid after DATACLK low delay
External DATACLK period
External DATACLK low
External DATACLK high
CS and R/C to external DATACLK setup time
18
19
90
40
20
5
19
10
20
12
83
60
18
83
1.4
1.1
75
600
20
400
100
40
50
25
15
Submit Documentation Feedback
相關PDF資料
PDF描述
ADS8507IB 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
ADS8507IBDW 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
ADS8507IBDWG4 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
ADS8507IBDWR 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
ADS8507IBDWRG4 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
相關代理商/技術參數(shù)
參數(shù)描述
ADS8507IB 制造商:BB 制造商全稱:BB 功能描述:16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
ADS8507IBDW 功能描述:模數(shù)轉換器 - ADC 16-Bit 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8507IBDWG4 功能描述:模數(shù)轉換器 - ADC 16-Bit 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8507IBDWR 功能描述:模數(shù)轉換器 - ADC 16-Bit 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8507IBDWRG4 功能描述:模數(shù)轉換器 - ADC 16-Bit 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*