參數(shù)資料
型號(hào)： ADS8507I
英文描述： 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
中文描述： 16位40 kSPS的低功耗采樣模擬到數(shù)字轉(zhuǎn)換的內(nèi)部基準(zhǔn)，并行/串行接口
文件頁數(shù)： 13/32頁
文件大小： 738K
代理商： ADS8507I
www.ti.com
READING DATA
The ADS8507 outputs serial or parallel data in straight binary (SB) or binary 2's complement data output format.
If SB/BTC (pin 7) is high, the output is in SB format, and if low, the output is in BTC format. Refer to
Table 4
for
ideal output codes. The first conversion immediately following a power-up does not produce a valid conversion
result.
ADS8507
SLAS381–DECEMBER 2006
CS and R/C are internally ORed and level triggered. It is not a requirement which input goes low first when
initiating a conversion. If, however, it is critical that CS or R/C initiates conversion
N
, be sure the less critical
input is low at least t
su2
≥
10 ns prior to the initiating input. If EXT/INT (pin 8) is low when initiating conversion
N
,
serial data from conversion
N–1
is output on SDATA (pin 19) following the start of conversion
N
. See Internal
Data Clock in the Reading Data section.
To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. This
has no effect when using the internal data clock in the serial output mode. The parallel output and the serial
output (only when using an external data clock), however, is affected whenever R/C goes high and the external
clock is active. Refer to the Reading Data section. In the internal clock mode data is clocked out every convert
cycle regardless of the states of CS and R/C. The conversion result is available as soon as BUSY returns to
high therefore, data always represents the conversion previously completed even when it is read during a
conversion.
The parallel output can be read without affecting the internal output registers; however, reading the data through
the serial port shifts the internal output registers one bit per data clock pulse. As a result, data can be read on
the parallel port prior to reading the same data on the serial port, but data cannot be read through the serial port
prior to reading the same data on the parallel port.
Table 3. Control Functions When Using Serial Output
(1)
CS
↓
0
↓
0
↓
R/C
0
↓
0
↓
1
BUSY
1
1
1
1
1
EXT/INT
0
0
1
1
1
DATACLK
Output
Output
Input
OPERATION
Initiates conversion
N
. Valid data from conversion
N–1
clocked out on SDATA.
Initiates conversion
N
. Valid data from conversion
N–1
clocked out on SDATA.
Initiates conversion
N
. Internal clock still runs conversion process.
Initiates conversion
N
. Internal clock still runs conversion process.
Conversion
N
completed. Valid data from conversion
N
clocked out on SDATA
synchronized to external data clock.
Valid data from conversion
N–1
output on SDATA synchronized to external data clock.
Conversion
N
in progress.
Valid data from conversion
N–1
output on SDATA synchronized to external data clock.
Conversion
N
in progress.
New conversion initiated without acquisition of a new signal. Data will be invalid. CS
and/or R/C must be HIGH when BUSY goes HIGH.
New convert commands ignored. Conversion
N
in progress..
Input
↓
1
0
1
Input
0
↑
0
1
Input
0
0
↑
X
Input
X
X
0
X
X
(1)
See
Figure 37
,
Figure 38
, and
Figure 39
for constraints on data valid from conversion
N–1
.
Table 4. Output Codes and Ideal Input Voltages
DIGITAL OUTPUT
DESCRIPTION
ANALOG INPUT
BINARY 2's COMPLEMENT
(SB/BTC LOW)
STRAIGHT BINARY (SB/BTC HIGH)
Full-scale range
±10
0 V to 5 V
0 V to 4 V
HEX
CODE
BINARY CODE
BINARY CODE
HEX CODE
Least significant bit (LSB)
305 μV
76 μV
61 μV
+Full-Scale (FS - 1LSB)
9.999695 V
4.999924 V
3.999939 V
0111 1111 1111 1111
7FFF
1111 1111 1111 1111
FFFF
Midscale
0 V
2.5 V
2 V
0000 0000 0000 0000
0000
1000 0000 0000 0000
8000
One LSB Below Midscale
305 μV
2.499924 V
1.999939 V
1111 1111 1111 1111
FFFF
0111 1111 1111 1111
7FFF
-Full-Scale
-10 V
0 V
0 V
1000 0000 0000 0000
8000
0000 0000 0000 0000
0000
13
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相關(guān)PDF資料
PDF描述
ADS8507IB 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
ADS8507IBDW 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
ADS8507IBDWG4 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
ADS8507IBDWR 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
ADS8507IBDWRG4 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS8507IB 制造商:BB 制造商全稱:BB 功能描述:16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
ADS8507IBDW 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8507IBDWG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8507IBDWR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8507IBDWRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 40KSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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