參數(shù)資料
型號(hào): ADS8481IBRGZRG4
英文描述: 18-BIT, 1-MSPS, PSEUDO-DIFFERENTIAL UNIPOLAR INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE
中文描述: 18位,1 MSPS的,偽差分單極輸入,微采樣模擬到數(shù)字轉(zhuǎn)換并行接口和參考
文件頁數(shù): 23/31頁
文件大?。?/td> 717K
代理商: ADS8481IBRGZRG4
www.ti.com
RESET
On power-up, internal POWER-ON RESET circuitry generates the reset required for the device. The first three
conversions after power-up are used to load factory trimming data for a specific device to assure high accuracy
of the converter. The results of the first three conversions are invalid and should be discarded.
ADS8481
SLAS385A–FEBRUARY 2006–REVISED MARCH 2006
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
Full scale range
Least significant bit (LSB)
+Full scale
Midscale
Midscale – 1 LSB
Zero
ANALOG VALUE
+V
ref
(+V
ref
)/262144
(+V
ref
) – 1 LSB
(+V
ref
)/2
(+V
ref
)/2 – 1 LSB
0 V
DIGITAL OUTPUT STRAIGHT BINARY
BINARY CODE
11 1111 1111 1111 1111
10 0000 0000 0000 0000
01 1111 1111 1111 1111
00 0000 0000 0000 0000
HEX CODE
3FFFF
20000
1FFFF
00000
The output data is a full 18-bit word (D17–D0) on DB17–DB0 pins (MSB–LSB) if both BUS18/16 and BYTE are
low.
The result may also be read on an 16-bit bus by using only pins DB17–DB2. In this case two reads are
necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 16 most significant bits
(D17–D2) on pins DB17–DB2, then bringing BUS18/16 high while holding BYTE low. When BUS18/16 is high,
the lower two bits (D1–D0) appear on pins DB3–DB2.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB17–DB10. In
this case three reads are necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 8
most significant bits on pins DB17–DB10, then bringing BYTE high while holding BUS18/16 low. When BYTE is
high, the medium bits (D9–D2) appear on pins DB17–DB10. The last read is done by bringing BUS18/16 high
while holding BYTE high. When BUS18/16 is high, the lower two bits (D1–D0) appear on pins DB11–DB10. The
last read cycle is not necessary if only the first 16 most significant bits are of interest.
All of these multiword read operations can be performed with multiple active RD (toggling) or with RD held low
for simplicity. This is referred to as the AUTO READ operation.
Table 2. Conversion Data Read Out
DATA READ OUT
PINS
DB9–DB4
All One's
All One's
All One's
D9–D4
BYTE
BUS18/16
PINS
PINS
PINS
DB3–DB2
All One's
D1–D0
All One's
D3–D2
PINS
DB1–DB0
All One's
All One's
All One's
D1–D0
DB17–DB12
All One's
All One's
D9–D4
D17–D12
DB11–DB10
D1–D0
All One's
D3–D2
D11–D10
High
Low
High
Low
High
High
Low
Low
The device can also be reset through the use of the combination fo CS and CONVST. Since the BUSY signal is
held at high during the conversion, either one of these conditions triggers an internal self-clear reset to the
converter.
Issue a CONVST when CS is low and the internal convert state is high. The falling edge of CONVST starts
a reset.
Issue a CS (select the device) while the internal convert state is high. The falling edge of CS causes a reset.
Once the device is reset, all output latches are cleared (set to zeroes) and the BUSY signal is brought low. A
new sampling period is started at the falling edge of the BUSY signal immediately after the instant of the internal
reset.
23
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ADS8481IPFBR 制造商:BB 制造商全稱:BB 功能描述:18-BIT, 1-MSPS, PSEUDO-DIFFERENTIAL UNIPOLAR INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE
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