參數(shù)資料
型號(hào): ADS8422IBPFBR
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48
封裝: 9 X 9 MM, GREEN, PLASTIC, TQFP-48
文件頁(yè)數(shù): 25/28頁(yè)
文件大?。?/td> 1310K
代理商: ADS8422IBPFBR
www.ti.com
TIMING CHARACTERISTICS FROM DIGITAL INPUTS
TIMING CHARACTERISTICS OF DIGITAL OUTPUTS
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
All specifications typical at –40
°C to 85°C, +VBD = 2.7 V to 5.25 V (1)(2)
PARAMETER
MIN
TYP
MAX
UNIT
CONVERSION AND ACQUISITION
t(ACQ)
Acquisition time, internal to device, not externally visible
70
ns
tw1
Pulse duration, CONVST low
20
ns
tw2
Pulse duration, CONVST high
100
ns
tp1
Period, CONVST
250
ns
tq1
Quiet time, last toggle of interface input signals during acquisition before CONVST falling (3)
30
ns
tq2
Quiet time, CONVST falling to first toggle of interface input signals (3)
10
ns
POWER DOWN
PD1 low for only ADC reset (no powerdown)
20
500
tw3
Pulse duration
PD1 low for ADC reset and also ADC powerdown
1500
ns
PD2 low pulse duration for REFOUT and COMMOUT buffers powerdown
1500
Pulse duration, all others unspecified
10
ns
(1)
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from after 90% of transition.
(2)
All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching
90% of transition.
(3)
Quiet time zones are for meeting performance and not functionality.
All specifications typical at –40
°C to 85°C, +VBD = 2.7 V to 5.25 V (1)(2)
PARAMETER
MIN
TYP
MAX
UNIT
CONVERSION AND ACQUISITION
t(CONV)
Conversion time, internal to device, not externally visible
180
ns
td1
Delay time, CONVST fall to conversion start (aperture delay)
3
ns
DATA READ OPERATION
td2
Delay time, CONVST low to data valid if CS = RD = 0
225
ns
td3
Delay time, data valid to BUSY low if CS = RD = 0
5
ns
td4
Delay time, RD (or CS) low to data valid
17
ns
td5
Delay time, BYTE toggle to data valid
20
ns
td6
Delay time, data three-state after RD (or CS) high
12
ns
POWER DOWN
td7
Delay time, PD1 low to BUSY rising
20
ns
Delay time, PD1 high to device operational (with PD2 held high)
5
s
td8
Delay time, PD2 high to REFOUT/COMMOUT valid
25
ms
Delay time, power up (after AVDD = 4.75 V)
25
ms
td9
Delay time, data three-state after PD1 low
1.5
s
(1)
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from after 90% of transition.
(2)
All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching
90% of transition.
6
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