參數(shù)資料
型號: ADS8413IRGZT
英文描述: 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER
中文描述: 16位,2 MSPS的LVDS串行接口,SAR類比數(shù)位轉(zhuǎn)換器
文件頁數(shù): 17/38頁
文件大小: 1197K
代理商: ADS8413IRGZT
www.ti.com
BUS_BUSY #1
RD #2
SYNC_O #1
SYNC_I #2
CLK_O #1
CLK_I #2
t
d16
LSB #1
LSB 1
#1
SDO #1
SDO #2
CS = 0
15R
16R
17R
18R
t
d15
BUSY_BUS #2 = 1
17R
18R
17F
CLK_O #2
SYNC_O #2
t
pd1
#1 DATA
LSB #1
LSB 1
#1
MSB
MSB 1
#2 DATA
CASCADE
ADS8413
SLAS490–OCTOBER 2005
Figure 12. Data Propagation from Device
n
to Device
n+1
in Daisy Chain Mode
As shown in
Figure 12
there is a propagation delay of t
pd1
from SYNC_I to SYNC_O or SDI to SDO. Note that
the data frames of all devices in the chain appear seamless at the last device output. The rising edge of
SYNC_O occurs at an interval of 16 clocks (or 8 clocks in BYTE mode); this can be used as a data frame sync.
The deserializer at the output of the last device can shift the data on every falling edge of the clock and it can
latch the parallel 16-bit word on the second rising edge of CLK_O (shown as 18R) after every rising edge of
SYNC_O.
Figure 13
shows the cascade connection. The signals shown with double lines are LVDS and the others are
CMOS. Cascade mode is selected by setting MODE_C/D = 1. Similar to daisy chain, the first device in the chain
is identified by selecting LAT_Y/N = 0. For all other devices in the chain LAT_Y/N = 1. See
Table 1
for more
details on device configuration. SDO, CLK_O, and SYNC_O are connected to the common bus. This means only
one device occupies the bus at a time, while LVDS drivers for all other devices 3-state. Unlike SDO and
SYNC_O, the clock cannot be switched out from device to device as the receiver requires a continuous clock. So
only device 1 outputs the clock and CLK_O of all other devices is 3-stated by appropriately setting M1+ and M1-
as listed in
Table 1
.
17
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