參數(shù)資料
型號： ADS8413IRGZT
英文描述： 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER
中文描述： 16位，2 MSPS的LVDS串行接口，SAR類比數(shù)位轉換器
文件頁數(shù)： 10/38頁
文件大小： 1197K
代理商： ADS8413IRGZT
www.ti.com
t
w2
Not less than t
to
avoid device entering
wait state
t
d4
t
d2
t
d3
CONVST
BUSY
Sample Phase
Conversion Phase
t
acq
t
cnv
Sample Phase
DATA READ OPERATION
The ADS8413 supports a 200-MHz serial LVDS interface for data read operation. The three signal LVDS
interface (SDO, CLK_O, and SYNC_O) is well suited for high-speed data transfers. An application with a single
device or multiple devices can be implemented with a daisy chain or cascade configuration. The following
sections discuss data read timing when a single device is used.
DATA READ FOR A SINGLE DEVICE (See Table 1 for Device Configuration)
ADS8413
SLAS490–OCTOBER 2005
DETAILED DESCRIPTION (continued)
Figure 2. Sample and Convert With No Wait or
Back to Back
(2 MSPS Throughput)
The device ends the sample phase and enters the conversion phase on the falling edge of CONVST (CSTART).
A high level on the BUSY output indicates an ongoing conversion. The device conversion time is fixed. The
falling edge of CONVST (CSTART) during the conversion phase aborts the ongoing conversion. A data read
after a conversion abort fetches invalid data. Valid data is only available after a sample phase and a conversion
phase has completed. The timing diagram for control with CSTART is similar to
Figure 1
and
Figure 2
.
Table 2
shows the equivalent timing for control with CONVST and CSTART.
Table 2. CONVST and CSTART Timing Control
TIMING CONTROL WITH CONVST
t
w1
t
w2
t
d1
t
d2
t
d3
TIMING CONTROL WITH CSTART
t
w3
t
w4
t
d5
t
d6
t
d7
For a single device, there are two possible read cycle starts: a data read cycle start during a wait or sample
phase or a data read cycle start at the end of a conversion phase. Read cycle end conditions can change
depending on MODE C/D selection.
Figure 3
explains the data read cycle. The details of a read frame start with
the two previous listed conditions and a read cycle end with MODE C/D selection are explained in
Figure 5
and
Figure 6
and
Figure 7
and
Figure 8
, respectively.
10
相關PDF資料
PDF描述
ADS8413IRGZTG4 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER
ADS8413IBRGZR 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER
ADS8413IBRGZRG4 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER
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相關代理商/技術參數(shù)
參數(shù)描述
ADS8413IRGZTG4 功能描述:模數(shù)轉換器 - ADC 16-bit Uni Diff In Smp rt 4.75-5.25V RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8422 制造商:BB 制造商全稱:BB 功能描述:16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE
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ADS8422IB 制造商:BB 制造商全稱:BB 功能描述:16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE
ADS8422IBPFBR 功能描述:模數(shù)轉換器 - ADC 16 Bit MSPS Parallel ADC w/Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
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