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參數(shù)資料
| 型號(hào)： | ADS8413IRGZT |
| 英文描述： | 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位，2 MSPS的LVDS串行接口，SAR類比數(shù)位轉(zhuǎn)換器 |
| 文件頁數(shù)： | 16/38頁 |
| 文件大?。?/td> | 1197K |
| 代理商： | ADS8413IRGZT |
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RD #1
BUS_BUSY
(Last device)
CS
16Bit Data
nth conversion
CONVST #1
nth CONV
n + 1 Tracking
n + 1 Conversion
BUS_BUSY #1
RD #2
SDO #1
SDI #2
t
d18
BUS_BUSY #2
RD #3
SYNC_O #1
SYNC_I #2
SDO #2
SDI #3
#1 16Bits
nth conversion
#2 16Bits
nth conversion
SYNC_O #2
SYNC_I #3
See Figure 6 for details
See Figure 12 for details
t
w5
ADS8413
SLAS490–OCTOBER 2005
Figure 11. Data Read Operation for Devices in Daisy Chain
DATA READ OPERATION
On power up, BUS_BUSY of all of the devices is low. The devices receive CONVST or CSTART to sample and
start the conversion. The first device in the chain starts the data read cycle at the end of its conversion.
BUS_BUSY of device 1 (connected to RD of device 2) goes high on the read cycle start. Device 2 BUS_BUSY
goes high on the rising edge of RD. This propagates until the last device in the chain. Device 2 receives CLK_I,
SDI, and SYNC_I from device 1 and it passes all of these signals to the next device. Device 2 (and every
subsequent device in the chain) passes the received signals to its output until it sees the falling edge of RD
(same as BUS_BUSY of the previous device). In daisy chain mode, BUS_BUSY for any device falls when it has
passed all of the previous device data followed by its own data. The falling edge of BUS_BUSY occurs before
the rising edge of SYNC_O. This indicates to the receiving device that the previous data chain is over and it is its
own turn to output the data. The device outputs the data from the last completed conversion. BUS_BUSY of the
last device in the chain is fed back to RD of the first device as shown in
Figure 10
(or device 1 RD tied to 0). This
makes sure that RD of device 1 is low before its conversion is over. The chain continues with only one external
signal (CONVST or CSTART) when CS is held low. Every device LVDS output goes to 3-state once all data
transfer through the device has been completed.
CS going high during the data read cycle of any device 3-states its SYNC_O and SDO. This halts the
propagation of data through the chain. To reset this condition it is necessary to assert CS high for all devices.
The new read sequence starts only after CS for all devices is low before point A as shown in
Figure 6
. The high
pulse on CS must be at least 20 ns wide. It is better to connect CS of all of the devices together to avoid
undesired halting of the daisy chain.
16
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| ADS8413IRGZTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-bit Uni Diff In Smp rt 4.75-5.25V RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8422 | 制造商:BB 制造商全稱:BB 功能描述:16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE |
| ADS8422EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 DATA CONVERTER RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS8422IB | 制造商:BB 制造商全稱:BB 功能描述:16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE |
| ADS8422IBPFBR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit MSPS Parallel ADC w/Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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