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| 型號(hào)： | ADS8406IPFBT |
| 英文描述： | 16-BIT, 1.25 MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE |
| 中文描述： | 16位，1.25 MSPS的，偽雙極，全差分輸入，微功耗采樣模擬到數(shù)字轉(zhuǎn)換并行接口 |
| 文件頁(yè)數(shù)： | 5/25頁(yè) |
| 文件大?。?/td> | 536K |
| 代理商： | ADS8406IPFBT |
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TIMING CHARACTERISTICS
All specifications typical at –40
°
C to 85
°
C, +VA = +VBD = 5 V
(1)(2)(3)
ADS8406
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
PARAMETER
MIN
500
150
TYP
MAX
650
UNIT
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
t
CONV
t
ACQ
t
pd1
t
pd2
t
w1
t
su1
t
w2
Conversion time
Acquisition time
CONVST low to BUSY high
Propagation delay time, end of conversion to BUSY low
Pulse duration, CONVST low
Setup time, CS low to CONVST low
Pulse duration, CONVST high
CONVST falling edge jitter
Pulse duration, BUSY signal low
Pulse duration, BUSY signal high
Hold time, First data bus data transition (RD low, or CS low for
read cycle, or BYTE input changes) after CONVST low
Delay time, CS low to RD low (or BUSY low to RD low when CS =
0)
Setup time, RD high to CS high
Pulse duration, RD low time
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, data hold from RD high
Delay time, BYTE rising edge or falling edge to data valid
Pulse duration, RD high
Pulse duration, CS high time
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
falling edge
Setup time, BYTE transition to RD falling edge
Hold time, BYTE transition to RD falling edge
Disable time, RD high (CS high for read cycle) to 3-stated data
bus
Delay time, end of conversion to MSB data valid
Byte transition setup time, from BYTE transition to next BYTE
transition
Delay time, CS rising edge to BUSY falling edge
Delay time, BUSY falling edge to CS rising edge
Setup time, from the falling edge of CONVST (used to start the
valid conversion) to the next falling edge of CONVST (when CS =
0 and CONVST used to abort) or to the next falling edge of CS
(when CS is used to abort)
Setup time, falling edge of CONVST to read valid data (MSB) from
current conversion
Hold time, data (MSB) from previous conversion hold valid from
falling edge of CONVST
40
5
20
0
20
10
t
w3
t
w4
Min(t
ACQ
)
610
t
h1
40
ns
t
d1
0
ns
t
su2
t
w5
t
en
t
d2
t
d3
t
w6
t
w7
0
ns
ns
ns
ns
ns
ns
ns
50
20
0
2
20
20
20
t
h2
50
ns
t
su3
t
h3
0
0
ns
ns
t
dis
20
ns
t
d5
10
ns
t
su4
50
ns
t
d6
t
d7
50
50
ns
ns
t
su(AB)
60
500
ns
t
su5
MAX(t
CONV
) + MAX(t
d5
)
ns
t
h4
MIN(t
CONV
)
ns
(1)
(2)
(3)
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
See timing diagrams.
All timings are measured with 20-pF equivalent loads on all data bits and BUSY pins.
5
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ADS8406IPFBTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 1.25 MSPS Pseudo Bipolar RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8406IPFFBR | 制造商:BB 制造商全稱:BB 功能描述:16-BIT, 1.25 MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE |
| ADS8410 | 制造商:BB 制造商全稱:BB 功能描述:16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE |
| ADS8410-13REF | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS8410-13REF Circuit Board RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS8410IBRGZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit Unipolar Pseudo Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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