參數(shù)資料
型號: ADS8406IPFBT
英文描述: 16-BIT, 1.25 MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE
中文描述: 16位,1.25 MSPS的,偽雙極,全差分輸入,微功耗采樣模擬到數(shù)字轉(zhuǎn)換并行接口
文件頁數(shù): 20/25頁
文件大?。?/td> 536K
代理商: ADS8406IPFBT
www.ti.com
DIGITAL INTERFACE
Timing And Control
Reading Data
ADS8406
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
See the timing diagrams in the specifications section for detailed information on timing signals and their
requirements.
The ADS8406 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8406 switches from
the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of
this signal is important to the performance of the converter. The BUSY output is brought high after CONVST
goes low. BUSY stays high throughout the conversion process and returns low when the conversion has ended.
Sampling starts as soon as the conversion is over when CS is tied low or starts with the falling edge of CS when
BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when
CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the
parallel output bus with the conversion.
The ADS8406 outputs full parallel data in two's complement format as shown in Table 1. The parallel output is
active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of
CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should
be attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is
used for multiword read operations. BYTE is used whenever lower bits of the converter result are output on the
higher byte of the bus. Refer to Table 1 for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
Full scale range
Least significant bit (LSB)
+Full scale
Midscale
Midscale – 1 LSB
– Full scale
ANALOG VALUE
2(+V
ref
)
2(+V
ref
)/65536
(+V
ref
) – 1 LSB
0 V
0 V– 1 LSB
( –V
ref
)
DIGITAL OUTPUT
2'S COMPLEMENT
BINARY CODE
0111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
HEX CODE
7FFF
0000
FFFF
8000
The output data is a full 16-bit word (D15–D0) on DB15–DB0 pins (MSB–LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15–DB8. In this
case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on
pins DB15–DB8, then bringing BYTE high. When BYTE is high, the low bits (D7–D0) appear on pins DB15–D8.
These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.
Conversion Data Readout
DATA READ OUT
DB7–DB0 Pins
All one's
D7–D0
BYTE
DB15–DB8 Pins
D7–D0
D15–D8
High
Low
20
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