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參數(shù)資料
| 型號： | ADS8406IPFBT |
| 英文描述： | 16-BIT, 1.25 MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE |
| 中文描述： | 16位，1.25 MSPS的，偽雙極，全差分輸入，微功耗采樣模擬到數(shù)字轉(zhuǎn)換并行接口 |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 536K |
| 代理商： | ADS8406IPFBT |
www.ti.com
RESET
RESET is an asynchronous active low input signal (that works independently of CS). Minimum RESET low time
is 25 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In
addition, all output latches are cleared (set to zero's) after RESET. The converter goes back to normal operation
mode no later than 20 ns after RESET input is brought high.
POWER-ON INITIALIZATION
RESET is not required after power on. An internal power-on-reset circuit generates the reset. To ensure that all
of the registers are cleared, the three conversion cycles must be given to the converter after power on.
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8406 circuitry.
ADS8406
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except
for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling
edge of CS, whichever is later.
Another way to reset the device is through the use of the combination of CS and CONVST. This is useful when
the dedicated RESET pin is tied to the system reset but there is a need to abort only the conversion in a specific
converter. Since the BUSY signal is held high during the conversion, either one of these conditions triggers an
internal self-clear reset to the converter just the same as a reset via the dedicated RESET pin. The reset does
not have to be cleared as for the dedicated RESET pin. A reset can be started with either of the two following
steps.
Issue a CONVST when CS is low and a conversion is in progress. The falling edge of CONVST must satisfy
the timing as specified by the timing parameter t
su(AB)
mentioned in the timing characteristics table to ensure
a reset. The falling edge of CONVST starts a reset. Timing is the same as a reset using the dedicated
RESET pin except the instance of the falling edge is replaced by the falling edge of CONVST.
Issue a CS while a conversion is in progress. The falling edge of CS must satisfy the timing as specified by
the timing parameter t
su(AB)
mentioned in the timing characteristics table to ensure a reset.The falling edge of
CS causes a reset. Timing is the same as a reset using the dedicated RESET pin except the instance of the
falling edge is replaced by the falling edge of CS.
As the ADS8406 offers single-supply operation, it is often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving
any single conversion for an n-bit SAR converter, there are at least n
windows
in which large external transient
voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby
digital logic, or high power devices.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the
external event.
On average, the ADS8406 draws very little current from an external reference, as the reference voltage is
internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive
the bypass capacitor or capacitors without oscillation. A 0.1-μF bypass capacitor and a 1-μF storage capacitor
are recommended from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the
same ground plane under the device.
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the
analog ground. Avoid connections which are close to the grounding point of a microcontroller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
21
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ADS8406IPFBTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 1.25 MSPS Pseudo Bipolar RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8406IPFFBR | 制造商:BB 制造商全稱:BB 功能描述:16-BIT, 1.25 MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE |
| ADS8410 | 制造商:BB 制造商全稱:BB 功能描述:16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE |
| ADS8410-13REF | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS8410-13REF Circuit Board RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS8410IBRGZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit Unipolar Pseudo Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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