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| 型號(hào)： | ADS8365IPAGRG4 |
| 英文描述： | 16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling SAR ANALOG-TO-DIGITAL CONVERTERS |
| 中文描述： | 16位，AD7691的6通道同步采樣SAR類(lèi)比數(shù)位轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 23/33頁(yè) |
| 文件大?。?/td> | 441K |
| 代理商： | ADS8365IPAGRG4 |
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NAP AND POWERDOWN MODE CONTROL
In order to minimize power consumption when the
ADS8365 is not in use, two low-power options are
available.
Nap
mode
minimizes
shutting down the biasing circuitry and internal
reference, allowing immediate recovery after it is
disabled. It can be enabled by either the NAP pin
going high, or setting DB6 in the data register high.
Enabling Powerdown mode results in lower power
consumption than Nap mode, but requires a short
recovery period after disabling. It can only be
enabled by setting DB5 in the data register high.
GETTING DATA
Flexible Output Modes: A0 A1, and A2.
t
ACQ
t
D1
t
D8
16
17
18
19
20
1
2
CLK
HOLD X
EOC
CS
RD
A0
t
D9
t
D7
ADS8365
SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006
B1, C0, and finally, C1 before reading A0 again.
Data from channel A0 are brought to the output first
after a reset signal, or after powering up the device.
The third mode is a FIFO mode that is addressed
with (A2, A1, A0 = 111). Data of the channel that is
converted first is read first. So, if a particular channel
pair is most interesting and is converted more
frequently (for example, to get a history of a
particular channel pair), then there are three output
registers per channel available to store data.
power
without
If all the output registers are filled up with unread
data and new data from an additional conversion
must be latched in, then the oldest data is discarded.
If a read process is going on (RD signal low) and
new data must be stored, then the ADS8365 waits
until the read process is finished (RD signal going
high) before the new data gets latched into its output
register. Again, with the ADD signal, it can be
chosen whether the address should be added to the
output data.
The ADS8365 has three different output modes that
are selected with A2, A1, and A0. The A2, A1 and
A0 pins are held with a transparent latch that triggers
on a falling edge of the RD pin negative-ANDed with
the CS pin (that is, if either RD or CS is low, the
falling edge of the other will latch A0-2).
New data is always written into the next available
register. At t
0
(see
Figure 31
), the reset deletes all
the existing data. At t
, the new data of the channels
A0 and A1 are put into registers 0 and 1. At t
2
, a
dummy read (RD low) is performed to latch the
address data correctly. At t
, the read process of
channel A0 data is finished; therefore, these data are
dumped and A1 data are shifted to register 0. At t
4
,
new data are available, this time from channels B0,
B1, C0, and C1. These data are written into the next
available registers (registers 1, 2, 3, and 4).
When (A2, A1, A0) = 000 to 101, a particular channel
can
be
directly
addressed
Figure 30
). The channel address should be set at
least 10ns (see
Figure 30
, t
D9
) before the falling edge
of RD and should not change as long as RD is low.
In this standard address mode, ADD will be ignored,
but should be connected to either ground or supply.
(see
Table
1
and
When (A2, A1, A0) = 110, the interface is running in
a cycle mode (see
Figure 29
). Here, data 7 down to
data 0 of channel A0 is read on the first RD signal,
and data 15 down to data 8 on the second as BYTE
is high. Then A1 on the second RD, followed by B0,
Figure 30. Timing for Reading Data
23
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| ADS8365M-EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 ADC CONVERTER RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類(lèi)型:ADC 工具用于評(píng)估:ADS130E08 接口類(lèi)型:SPI 工作電源電壓:- 6 V to + 6 V |
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