參數(shù)資料
型號: ADS8365IPAGRG4
英文描述: 16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling SAR ANALOG-TO-DIGITAL CONVERTERS
中文描述: 16位,AD7691的6通道同步采樣SAR類比數(shù)位轉(zhuǎn)換器
文件頁數(shù): 21/33頁
文件大?。?/td> 441K
代理商: ADS8365IPAGRG4
www.ti.com
Reading data (RD and CS)
BYTE
CS
RD
BYTE
A0
A1
A1
B0
B0
B1
C0
C1
A0
HIGH
A0
LOW
HIGH
HIGH
LOW
LOW
D7 – D0
ADS8365
SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006
CS being low tells the ADS8365 that the bus on the
board is assigned to the ADS8365. If an ADC shares
a bus with digital gates, there is a possibility that
digital (high-frequency) noise will be coupled into the
ADC. If the bus is just used by the ADS8365, CS can
be hardwired to ground. Reading data at the falling
edge of one of the HOLDX signals might cause
noise.
In general, the channel/data outputs are in tri-state.
Both CS and RD must be low to enable these
outputs. RD and CS must stay low together for at
least 40ns (see
Figure 1
, t
D6
) before the output data
are valid. RD must remain HIGH for at least 30ns
(see
Figure 1
, t
) before bringing it back low for a
subsequent read command.
The new data are latched into its output register 16.5
clock cycles after the start of a conversion (next
rising edge of clock after the falling edge of HOLDX).
Even if the ADS8365 is forced to wait until the read
process is finished (RD signal going high) before the
new data are latched into its output register, the
possibility still exists that the new data was latched to
the output register just before the falling edge of RD.
If a read process is initiated around 16.5 clock cycles
after the conversion started, RD and CS should stay
low for at least 50ns (see
Figure 1
, t
) to get the
new data stored to its register and switched to the
output.
If there is only an 8-bit bus available on a board,
then BYTE can be set high (see
Figure 29
). In this
case, the lower eight bits can be read at the output
pins D15 to D8 or D7 to D0 at the first RD signal,
and the higher bits after the second RD signal. If the
ADS8365 is used in the cycle or the FIFO mode,
then the address and data valid information is added
to the data (if ADD is high). In this case, the address
will be read first, then the lower eight bits, and finally
the higher eight bits. If BYTE is low, then the
ADS8365 operates in the 16-bit output mode. Here,
data are read between pins DB15 and DB0. As long
as ADD is low, with every RD impulse, data from a
new channel are brought to the output. If ADD is high
and the cycle or the FIFO mode is chosen; the first
output word contains the address, while the second
output word contains the 16-bit data.
Figure 29. Reading Data in Cycling Mode
21
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