參數(shù)資料
型號: ADS8365IPAGRG4
英文描述: 16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling SAR ANALOG-TO-DIGITAL CONVERTERS
中文描述: 16位,AD7691的6通道同步采樣SAR類比數(shù)位轉(zhuǎn)換器
文件頁數(shù): 22/33頁
文件大?。?/td> 441K
代理商: ADS8365IPAGRG4
www.ti.com
ADD Signal
Soft Trigger Mode
ADS8365
SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006
If conversion timing between ADCs is not critical,
Soft Trigger mode can allow all three HOLDX signals
to be triggered simultaneously. This simultaneous
triggering can be done by tying all three HOLDX pins
high, and issuing a write (CS and WR low) with the
DB0, DB1, DB2, and DB7 bits low, and the reset bit
(DB3) high. Writing a low to the reset bit (DB3) while
the RESET pin is high forces a device reset, and all
HOLDX signals that occur during that time are
ignored.
In the cycle and the FIFO mode, it might be desirable
to have address information with the 16-bit output
data. Therefore, ADD can be set high. In this case,
two RD signals (or three readings if the part is
operated with BYTE being high) are necessary to
read data of one channel, while the ADS8365
provides channel information on the first RD signal
(see
Table 2
and
Table 3
).
The HOLDX signals start conversion automatically
on the next clock cycle. The format of the two words
that can be written to the ADS8365 are shown in
Table 4
.
Signals NAP, ADD, A0, A1, A2, RESET, HOLDA,
HOLDB, and HOLDC are accessible through the
data bus and control word. Bits NAP, ADD, A0, A1
and A2 are in an
OR
configuration with hardware
pins. When software configuration is used, these
pins must be connected to ground. Conversely, the
RESET, HOLDA, HOLDB, and HOLDC bits are in a
NAND configuration with the hardware pins. When
software configuration is used, these pins must be
connected to BV
DD
.
Bits DB5 and DB4 do not have corresponding
hardware pins. Bit DB5 = 1 enables Powerdown
mode. Bit DB4 = 1 inverts the MSB of the output
data, putting the output data in two's complement
format. When DB4 is low, the data is in straight
binary format.
Table 2. Overview of the Output Formats Depending on Mode When ADD = 0
ADD = 0
A2 A1 A0
000
001
010
011
100
101
110
111
BYTE = 0
BYTE = 1
2nd RD
DB15...DB8
DB15...DB8
DB15...DB8
DB15...DB8
DB15...DB8
DB15...DB8
DB15...DB8
DB15...DB8
1st RD
DB15...DB0
DB15...DB0
DB15...DB0
DB15...DB0
DB15...DB0
DB15...DB0
DB15...DB0
DB15...DB0
2nd RD
No 2nd RD
No 2nd RD
No 2nd RD
No 2nd RD
No 2nd RD
No 2nd RD
No 2nd RD
No 2nd RD
1st RD
DB7...DB0
DB7...DB0
DB7...DB0
DB7...DB0
DB7...DB0
DB7...DB0
DB7...DB0
DB7...DB0
3rd RD
No 3rd RD
No 3rd RD
No 3rd RD
No 3rd RD
No 3rd RD
No 3rd RD
No 3rd RD
No 3rd RD
Table 3. Overview of the Output Formats Depending on Mode When ADD = 1
ADD = 1
A2 A1 A0
000
001
010
011
100
101
110
111
BYTE = 0
BYTE = 1
1st RD
DB15...DB0
DB15...DB0
DB15...DB0
DB15...DB0
DB15...DB0
DB15...DB0
2nd RD
No 2nd RD
No 2nd RD
No 2nd RD
No 2nd RD
No 2nd RD
No 2nd RD
DB15...DB0
DB15...DB0
1st RD
DB7...DB0
DB7...DB0
DB7...DB0
DB7...DB0
DB7...DB0
DB7...DB0
2nd RD
DB15...DB8
DB15...DB8
DB15...DB8
DB15...DB8
DB15...DB8
DB15...DB8
DB7...DB0
DB7...DB0
3rd RD
No 3rd RD
No 3rd RD
No 3rd RD
No 3rd RD
No 3rd RD
No 3rd RD
DB15...DB8
DB15...DB8
1000 0000 0000 DV A2 A1 A0
1000 0000 0000 DV A2 A1 A0
DV A2 A1 A0 DB3 DB2 DB0
DV A2 A1 A0 DB3 DB2 DB0
Table 4. Control Register Bits
DB7 (MSB)
1
0
DB6
NAP
X
DB5
PD
X
DB4
DB3
ADD
RESET
DB2
A2
HOLDA
DB1
A1
HOLDB
DB0 (LSB)
A0
HOLDC
Invert MSB
X
22
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