- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10707 > ADS8364Y/250 (Texas Instruments)IC ADC LP 16BIT 250KSPS 64TQFP PDF資料下載
參數(shù)資料
| 型號： | ADS8364Y/250 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC LP 16BIT 250KSPS 64TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 6 |
| 功率耗散（最大）： | 471.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（10x10） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 12 個單端，雙極；6 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 893 (CN2011-ZH PDF) |
| 配用： | 296-30708-ND - EVAL MODULE FOR ADS8364 ADS8364EVM-ND - EVALUATION MODULE FOR BQ2018 |
| 其它名稱： | 296-13449-6 |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
ADS8364
14
SBAS219C
www.ti.com
FIGURE 9. Timing for Reading Data.
register, the possibility still exists that the new data was
latched to the output register just before the falling edge of
RD. If a read process is initiated around 16.5 clock cycles
after the conversion started, RD and CS should stay LOW
for at least 50ns (see Timing Diagram, tW6) to get the new
data stored to its register and switched to the output.
CS being LOW tells the ADS8364 that the bus on the board
is assigned to the ADS8364. If an ADC shares a bus with
digital gates, there is a possibility that digital (high-frequency)
noise will be coupled into the ADC. If the bus is just used by
the ADS8364, CS can be hardwired to ground. Reading data
at the falling edge of one of the HOLDX signals might cause
noise.
BYTE—If there is only an 8-bit bus available on a board,
then BYTE can be set HIGH. (see Figure 11) In this case, the
lower 8 bits can be read at the output pins D15 to D8 or D7
to D0 at the first RD signal and the higher bits after the
second RD signal. If the ADS8364 is used in the cycle or the
FIFO mode, then the address and a data valid information is
added to the data if ADD is HIGH. In this case, the address will
be read first, then the lower 8 bits, and finally the higher 8 bits.
FIGURE 8. Timing of one Conversion Cycle.
If BYTE is LOW, then the ADS8364 operates in the 16-bit
output mode. Here, data is read between the pins DB15 and
DB0. As long as ADD is LOW, with every RD-impulse, data
from a new channel is brought to the output. If ADD is HIGH,
and the cycle or the FIFO mode is chosen; the first output
word will contain the address, while the second output word
contains the 16-bit data.
ADD-Signal–In the cycle and the FIFO mode, it might be
desirable to have address information with the 16-bit output
data. Therefore, ADD can be set HIGH. In this case, two (or
three readings if the part is operated with byte being HIGH)
RD-signals are necessary to read data of one channel, while
the ADS8364 provides channel information on the first RD
signal (see Table III and Table IV).
The signals ADD, A0, A1, A2, RESET, HOLDA, HOLDB,
and HOLDC are accessible through the data bus and control
word. All these pins are in OR configuration with hardware
pins. When software configuration is used, the correspond-
ing pins must be connected to ground or the power supply.
When the MSB is HIGH, the device is in the configuration
mode. MSB LOW will start conversion or reset the part.
1
2
16
17
18
19
20
1
2
CONVERSION
ACQUISITION
CLK
HOLD B
EOC
CS
RD
A0
t
ACQ
t
D1
t
D8
t
W7
16
17
18
19
20
1
2
CLK
HOLD X
EOC
CS
RD
A0
t
D9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-J1N-MY-F1 | CONVERTER MOD DC/DC 18.5V 50W |
| VI-BTW-MY-B1 | CONVERTER MOD DC/DC 5.5V 50W |
| VI-J1N-MY-F4 | CONVERTER MOD DC/DC 18.5V 50W |
| VI-BTV-MY-B1 | CONVERTER MOD DC/DC 5.8V 50W |
| FIN1019MX | IC DRVR/RCVR 3.3V HS LVDS 14SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS8365 | 制造商:BB 制造商全稱:BB 功能描述:16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling SAR ANALOG-TO-DIGITAL CONVERTERS |
| ADS8365IPAG | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16B 250kSPS 6Ch Simu Sampling SAR ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8365IPAGG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16B 250kSPS 6Ch Simu Sampling SAR ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8365IPAGG-4 | 制造商:Texas Instruments 功能描述:IC, SM 16-BIT ADC 6CH SAR |
| ADS8365IPAGR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 B 250k SPS 6 Ch Smltns Smplg SARADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。