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參數(shù)資料
| 型號(hào)： | ADS8364Y/250 |
| 廠商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 4/26頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC LP 16BIT 250KSPS 64TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 6 |
| 功率耗散（最大）： | 471.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（10x10） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類(lèi)型： | 12 個(gè)單端，雙極；6 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁(yè)面： | 893 (CN2011-ZH PDF) |
| 配用： | 296-30708-ND - EVAL MODULE FOR ADS8364 ADS8364EVM-ND - EVALUATION MODULE FOR BQ2018 |
| 其它名稱： | 296-13449-6 |
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ADS8364
12
SBAS219C
www.ti.com
TIMING AND CONTROL
The ADS8364 uses an external clock (CLK, pin 28) which
controls the conversion rate of the CDAC. With a 5MHz
external clock, the ADC sampling rate is 250kSPS which
corresponds to a 4
s maximum throughput time. Acquistion
and conversion takes a total of 20 clock cycles.
THEORY OF OPERATION
The ADS8364 contains six 16-bit ADCs that can operate
simultaneously in pairs. The three hold signals (HOLDA,
HOLDB, and HOLDC) initiate the conversion on the specific
channels. A simultaneous hold on all six channels can occur
with all three hold signals strobe together. The converted
values are saved in six registers. For each read operation,
the ADS8364 outputs 16 bits of information (16 Data or 3
Channel Address, Data Valid, and some synchronization
information). The Address/Mode signals (A0, A1, and A2)
select how the data is read from the ADS8364. These
Address/Mode signals can define a selection of a single
channel, a cycle mode that cycles through all channels, or a
FIFO mode that sequences the data determined by the order
of the hold signals. The FIFO mode will allow the six registers
to be used by a single-channel pair and, therefore, three
locations for CH X0 and three locations for CH X1 can be
updated before they are read from the part.
EXPLANATION OF CLOCK, RESET, FD, AND EOC PINS
Clock—An external clock has to be provided for the ADS8364.
The maximum clock frequency is 5MHz. The minimum clock
cycle is 200ns (Timing Diagram, tC1), and the clock has to remain
HIGH (Timing Diagram, tW1) or LOW for at least 60ns.
RESET—Bringing reset signal LOW will reset the ADS8364.
It will clear all the output registers, stop any actual conver-
sions, and will close the sampling switches. The reset signal
has to stay LOW for at least 20ns (see Figure 7, tW4). The
reset signal should be back HIGH for at least 20ns (see
Figure 7, tD2), before starting the next conversion (negative
hold edge).
current into the ADS8364 charges the internal capacitor
array during the sampling period. After this capacitance has
been fully charged, there is no further input current. The
source of the analog input voltage must be able to charge the
input capacitance (25pF) to a 16-bit settling level within 3
clock cycles if the minimum acquisition time is used. When
the converter goes into the hold mode, the input impedance
is greater than 1G
.
Care must be taken regarding the absolute analog input
voltage. The +IN and –IN inputs should always remain within
the range of AGND – 0.3V to AVDD + 0.3V.
TRANSITION NOISE
The transition noise of the ADS8364 itself is low,
as shown in Figure 5. These histograms were generated by
applying a low-noise DC input and initiating 8000 conversions.
The digital output of the ADC will vary in output code due to
the internal noise of the ADS8364. This is true for all 16-bit,
SAR-type ADCs. Using a histogram to plot the output codes,
the distribution should appear bell-shaped with the peak of the
bell curve representing the nominal code for the input value.
The
±1σ, ±2σ, and ±3σ distributions will represent the 68.3%,
95.5%, and 99.7%, respectively, of all codes. The transition
noise can be calculated by dividing the number of codes
measured by 6 and this will yield the
±3σ distribution, or
99.7%, of all codes. Statistically, up to three codes could fall
outside the distribution when executing 1000 conversions.
Remember, to achieve this low-noise performance, the peak-
to-peak noise of the input signal and reference must be
< 50
V.
FIGURE 5. 8000 Conversion Histogram of a DC Input.
FIGURE 6. Level Shift Circuit for Bipolar Input Ranges.
BIPOLAR INPUTS
The differential inputs of the ADS8364 were designed to accept
bipolar inputs (–VREF and +VREF) around the common-mode
voltage (2.5V), which corresponds to a 0V to 5V input range with
a 2.5V reference. By using a simple op amp circuit featuring
four, high-precision external resistors, the ADS8364 can be
configured to accept bipolar inputs. The conventional
±2.5V,
±5V, and ±10V input ranges could be interfaced to the ADS8364
using the resistor values shown in Figure 6.
32807 32808
2726
32805
720
32804
167
32806
680
813
32812
67
32810
32809
906
930
1183
32811
Code
0
32803
0
32813
R
1
R
2
+IN
–IN
REF
OUT (pin 61)
2.5V
4k
20k
Bipolar Input
BIPOLAR INPUT
R
1
R
2
±10V
1k
5k
±5V
2k
10k
±2.5V
4k
20k
OPA227
ADS8364
OPA227
1.2k
1.2k
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| ADS8365 | 制造商:BB 制造商全稱:BB 功能描述:16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling SAR ANALOG-TO-DIGITAL CONVERTERS |
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| ADS8365IPAGG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16B 250kSPS 6Ch Simu Sampling SAR ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8365IPAGG-4 | 制造商:Texas Instruments 功能描述:IC, SM 16-BIT ADC 6CH SAR |
| ADS8365IPAGR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 B 250k SPS 6 Ch Smltns Smplg SARADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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