
ADS809
SBAS170C
16
www.ti.com
FIGURE 13. Recommended Supply Decoupling Scheme.
feed back to the analog portion of the ADS809 and adversely
affect the performance. External buffers, or latches, close to
the converter
’
s output pins may be used to minimize the
capacitive loading. They also provide the added benefit of
isolating the ADS809 from any digital activities on the bus
from coupling back high-frequency noise.
POWER SUPPLIES
When defining the power supplies for the ADS809, is it highly
recommended to consider linear supplies instead of switch-
ing types. Even with good filtering, switching supplies may
radiate noise that could interfere with any high-frequency
input signal and cause unwanted modulation products. At its
full conversion rate of 80MHz, the ADS809 requires typically
170mA of supply current on the +5V supply (+V
S
). Note that
this supply voltage should stay within a 5% tolerance. The
ADS809 does not require separate analog and digital sup-
plies, but only one single +5V supply to be connected to all
its +V
S
pins. This is with the exception of the output driver
supply pin, denoted VDRV (see the following section).
Digital Output Driver Supply (VDRV)
A dedicated supply pin, denoted VDRV, provides power to
the logic output drivers of the ADS809, and may be operated
with a supply voltage in the range of +3.0V to +5.0V. This can
simplify interfacing to various logic families, in particular low-
voltage CMOS. It is recommended to operate the ADS809
with a +3.0V supply voltage on VDRV. This will lower the
power dissipation in the output stages due to the lower output
swing and reduce current glitches on the supply line that may
affect the AC performance of the converter. The analog
supply (+V
S
) and driver supply (VDRV) may be tied together,
with a ferrite bead or inductor between the supply pins. Each
of the these supply pins must be bypassed separately with at
least one 0.1
μ
F ceramic chip capacitor, forming a pi-filter.
The recommended operation for the ADS809 is +5V for the
+V
S
pins and +3.0V on the output driver pin (VDRV).
LAYOUT AND DECOUPLING CONSIDERATIONS
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high-
frequency designs. Achieving optimum performance with a
fast sampling converter, like the ADS809, requires careful
attention to the pc-board layout to minimize the effect of
board parasitics and optimize component placement.
A multilayer board usually ensures best results and allows
convenient component placement.
The ADS809 should be treated as an analog component with
the +V
S
pins connected to clean analog supplies. This will
ensure the most consistent results, since digital supplies
often carry a high level of switching noise that could couple
into the converter and degrade the performance. As men-
tioned previously, the driver supply pins (VDRV) should also
be connected to a low-noise supply. Supplies of adjacent
digital circuits may carry substantial current transients. The
supply voltage must be thoroughly filtered before connecting
to the VDRV supply of the converter. All ground connections
on the ADS809 are internally bonded to the metal flag
(bottom of package) that forms a large ground plane. All
ground pins should directly connect to an analog ground
plane that covers the pc-board area under the converter.
Because of its high sampling frequency, the ADS809 gener-
ates high-frequency current transients and noise (clock
feedthrough) that are fed back into the supply and reference
lines. If not sufficiently bypassed, this will add noise to the
conversion process. Figure 13 shows the recommended
supply decoupling scheme for the ADS809. All +V
S
pins may
be connected together and bypassed with a combination of
10nF to 0.1
μ
F ceramic chip capacitors (0805, low ESR) and
a 10
μ
F tantalum tank capacitor. A similar approach may be
used on the driver supply pins, VDRV. In order to minimize
the lead and trace inductance, the capacitors should be
located as close to the supply pins as possible. Where
double-sided component mounting is allowed, they are best
placed directly under the package. In addition, larger bipolar
decoupling capacitors (2.2
μ
F to 10
μ
F), effective at lower
frequencies, should also be used on the main supply pins.
They can be placed on the pc-board in proximity (< 0.5") of
the ADC.
+V
2, 47, 48
35, 36, 37, 38
42, 43, 45
GND
ADS809
0.1
μ
F
0.01
μ
F
0.01
μ
F
0.01
μ
F
+V
S
3, 4
5, 8, 31
GND
0.1
μ
F
VDRV
26
9, 27
GND
0.1
μ
F
+3V, +5V
+5V
If the analog inputs to the ADS809 are driven differentially, it
is especially important to optimize towards a highly symmetri-
cal layout. Small trace length differences may create phase
shifts compromising a good distortion performance. For this
reason, the use of two single op amps (rather than one dual
amplifier) enables a more symmetrical layout and a better
match of parasitic capacitances. The pin orientation of the
ADS809 package follows a
“
flow-through
”
design with the
analog inputs located on one side of the package while the
digital outputs are located on the opposite side of the quad-
flat package. This provides a good physical isolation be-