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參數(shù)資料
| 型號(hào)： | ADS809 |
| 英文描述： | 12-Bit, 80MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 12位，80MHz的采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 437K |
| 代理商： | ADS809 |
ADS809
SBAS170C
15
www.ti.com
CLK
CLK
ADS809
1:1
R
T
RF Sine
Source
Depending on the nature of the clock source
’
s output imped-
ance, an impedance matching might become necessary. For
this, a termination resistor (R
T
) may be installed, as shown in
Figure 12. To calculate the correct value for this resistor,
consider the impedance ratio of the selected transformer and
the differential clock input impedance of the ADS809, which
is approximately 5.4k
.
It is not recommended to employ any type of differential TTL
logic that suffers from mismatch in delay time and slew-rate
leading to performance degradation. Alternatively, a low jitter
ECL or PECL clock may be AC-coupled directly to the clock
inputs using small (0.1
μ
F) capacitors.
Output Enable (
OE
)
The digital outputs of the ADS809 can be set to high
impedance (tri-state), exercising the output enable pin (
OE
).
For normal operation, this pin must be at a logic LOW
potential while a logic HIGH voltage disables the outputs.
Even though this function effects the output driver stage, the
threshold voltages for the
OE
pin do not depend on the
output driver supply (VDRV), but are fixed (see
“
Specifica-
tions, Digital Inputs
”
). Operating the
OE
function dynamically
(i.e., high-speed multiplexing, should be avoided, as it will
corrupt the conversion process.
Power Down (PD)
A power-down of the ADS809 is initiated by taking the PD pin
HIGH. This shuts down portions within the converter and
reduces the power dissipation to about 20mW. The remain-
ing active blocks include the internal reference, ensuring a
fast reactivation time. During power-down, data in the con-
verter pipeline will be lost and new valid data will be subject
to the specified pipeline delay. In case the PD pin is not used,
it should be tied to ground or a logic LOW level.
Over-Range Indicator (OVR)
If the analog input voltage exceeds the full-scale range set by
the reference voltages, an over-range condition exists. The
ADS809 incorporates a function that monitors the input
voltage and detects any such out-of-range condition. The
current state can be read at the over-range indicator pin
(OVR). This output is LOW when the input voltage is within
the defined input range. It will change to HIGH if the applied
signal exceeds the full-scale range. It should be noted that
the OVR output is updated along with the data output,
corresponding to the particular sampled analog input volt-
age. Therefore, the OVR data is subject to the same pipeline
delay as the digital data (5 clock cycles).
Output Loading
It is recommended to keep the capacitive loading on the data
output lines as low as possible, preferably below 15pF.
Higher capacitive loading will cause larger dynamic currents
to flow as the digital outputs are changing. For example, with
a typical output slew-rate of 0.8V/ns and a total capacitive
loading of 10pF (including 4pF output capacitance, 5pF input
capacitance of external logic buffer, and 1pF pc-board
parasitics), a bit transition can cause a dynamic current of
(10pF
0.8V/1ns = 8mA). Those high current surges can
FIGURE 12. Applying a Sinusoidal Clock to the ADS809.
MINIMUM SAMPLING RATE
The pipeline architecture of the ADS809 uses the switched
capacitor technique in its internal track-and-hold stages. With
each clock cycles charges representing the captured signal
level are moved within the ADC pipeline core. The high
sampling speed necessitates the use of very small capacitor
values. In order to hold the droop errors LOW, the capacitors
require a minimum
“
refresh rate.
”
Therefore, the sampling
clock on the ADS809 should not drop below the specified
minimum of 1MHz.
DATA OUTPUT FORMAT (BTC)
The ADS809 makes two data output formats available, either
the
“
Straight Offset Binary
”
code (SOB) or the
“
Binary Two
’
s
Complement
”
code (BTC). The selection of the output coding
is controlled through the BTC pin. Applying a logic HIGH will
enable the BTC coding, while a logic LOW will enable the
SOB code. The BTC output format is widely used to interface
to microprocessors and such. The two code structures are
identical with the exception that the MSB is inverted for the
BTC format, as shown in Tables II and III.
BINARY TWO
’
S
COMPLEMENT
(BTC)
STRAIGHT OFFSET
BINARY (SOB)
DIFFERENTIAL INPUT
+FS
–
1LSB
(IN = +3V,
IN
= +2V)
+1/2 FS
Bipolar Zero
(IN =
IN
= CMV)
–
1/2 FS
–
FS
(IN = +2V,
IN
= +3V)
1111 1111 1111
0111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0000
0100 0000 0000
0000 0000 0000
1100 0000 0000
1000 0000 0000
TABLE III. Coding Table for Differential Input Configuration
and 2Vp-p Full-Scale Input Range.
BINARY TWO
’
S
COMPLEMENT
(BTC)
STRAIGHT OFFSET
BINARY (SOB)
DIFFERENTIAL INPUT
+FS
–
1LSB
(
IN
= CMV + FSR/2)
+1/2 FS
Bipolar Zero
(IN = CMV)
–
1/2 FS
–
FS
(IN = CMV
–
FSR/2)
1111 1111 1111
0111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0000
0100 0000 0000
0000 0000 0000
1100 0000 0000
1000 0000 0000
TABLE II. Coding Table for Singles-Ended Input Configuration
with IN Tied to the Common-Mode Voltage (CMV).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS809Y/250 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 80MHz Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS809Y/250G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 80MHz Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS809Y/2K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 80MHz Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS809Y/2K5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A/D CONVERTER |
| ADS809Y/2KG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 80MHz Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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