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參數(shù)資料
| 型號： | ADS7863 |
| 英文描述： | Dual, 1.5MSPS, 12-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 雙路，1.5Msps的，12位，2通道，同步采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大?。?/td> | 637K |
| 代理商： | ADS7863 |
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P
MODE I
C[1:0] = '11'
P[1:0] = '11'
Convert CHx1 Next
SDI Features Not Used
C[1:0] = '00'
P[1:0] = '00'
Convert CHx0 Next
SDI Features Not Used
C[1:0] = '00'
P[1:0] = '00'
Convert CHx0 Next
SDI Features Not Used
0 0
Previous 12-Bit Data CHAx
12-Bit Data CHA1
High-Z
High-Z
12-Bit Data CHB1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Previous Conversion of Both CHxx
Conversion of Both CHx1
Conversion of Both CHx0
1.0 s
m
0.5 s
m
0 s
m
1
16 1
16
CLOCK
CONVST
SDI
M0
M1
RD
CS
SDOA
SDOB
BUSY
Previous 12-Bit Data CHBx
ADS7863
SBAS383–JUNE 2007
Additionally, the SDI pin is used for controlling device
functionality; see the
Serial Data Input
section for
details.
16 clock cycles are required to perform a single
conversion. With the rising edge of CONVST, the
ADS7863 switches asynchronously to the external
CLOCK from sample to hold mode.
Converted data on the SDOx pins becomes valid
with the third falling CLOCK edge after generating an
RD pulse. The following sections explain the four
different modes of operation in detail.
After some delay (t
12
), the BUSY output pin goes
high and remains high for the duration of the
conversion cycle. On the falling edge of the second
CLOCK cycle, the ADS7863 latches in the channel
for the next conversion cycle, depending on the
status of the SDI pin. CS must be brought low to
enable both serial outputs. Data are valid on the
falling edge of every 16 clock cycles per conversion.
The first two bits are set to '0'. The subsequent data
contain
the
12-bit
conversion
significant bit is transferred first), followed by two '0's
(see
Figure 1
and
Figure 16
).
With the M0 and M1 pins both set to '0', the
ADS7863 enters manual channel control operation.
The SDI pin is used to switch between the channels.
A conversion is initiated by bringing CONVST high.
result
(the
most
Figure 16. Mode I Timing Diagram (M0 = 0; M1 = 0)
14
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS7863I | Dual, 1.5MSPS, 12-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7863IDBQ | Dual, 1.5MSPS, 12-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7863IDBQR | Dual, 1.5MSPS, 12-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7863IRGE | Dual, 1.5MSPS, 12-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7863IRGER | Dual, 1.5MSPS, 12-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7863_08 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Dual, 2MSPS, 12-Bit, 2 + 2 or 3 + 3 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7863ADBQ | 功能描述:ANALOG TO DIGITAL CONVERTERS - A 制造商:texas instruments 系列:* 包裝:管件 零件狀態(tài):在售 封裝/外殼:24-SSOP（0.154"，3.90mm 寬） 供應(yīng)商器件封裝:24-SSOP 標(biāo)準(zhǔn)包裝:50 |
| ADS7863ADBQR | 制造商:Texas Instruments 功能描述:IC ADC 12BIT SER 2M 24QSOP |
| ADS7863ARGER | 功能描述:ANALOG TO DIGITAL CONVERTERS - A 制造商:texas instruments 系列:* 包裝:帶卷（TR） 零件狀態(tài):在售 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商器件封裝:24-VQFN（4x4） 標(biāo)準(zhǔn)包裝:3,000 |
| ADS7863ARGET | 制造商:Texas Instruments 功能描述:IC ADC 12BIT DUAL 2MSPS 24-VQFN |
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