參數(shù)資料
型號: ADS7863
英文描述: Dual, 1.5MSPS, 12-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述: 雙路,1.5Msps的,12位,2通道,同步采樣模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 11/30頁
文件大?。?/td> 637K
代理商: ADS7863
www.ti.com
P
APPLICATIONS INFORMATION
GENERAL DESCRIPTION
The ADS7863 includes two 12-bit analog-to-digital
converters
(ADCs)
that
successive-approximation register (SAR) principle.
The ADCs sample and convert simultaneously.
Conversion time can be as low as 541.67ns. Adding
the acquisition time of 125ns results in a maximum
conversion rate of 1.5MSPS.
Input
MUX
ADC+
ADC
-
CHx1+
CHx1
-
CHx0+
CHx0
-
ANALOG
This section addresses the analog input circuit, the
ADCs, and the reference design of the device.
Analog Inputs
f
=
-
3dB
ln(2)
(n + 1)
2
t
p ′
ACQ
(1)
ADS7863
SBAS383–JUNE 2007
operate
based
on
the
Figure 15. Input Multiplexer Configuration
Each ADC has a fully differential, 2:1 multiplexer
front-end. In many common applications, all negative
input signals remain at the same constant voltage
(for example, 2.5V). In this type of application, the
multiplexer can be used in a pseudo-differential 3:1
mode, where CHx0– functions as a common pin and
the remaining three inputs (CHx0+, CHx1–, and
CHx1+) operate as separate inputs referred to the
common pin.
Table 1. Fully Differential 2:1 Multiplexer
Configuration
C1
0
1
C0
0
1
ADC+
CHx0+
CHx1+
ADC–
CHx0–
CHx1–
Table 2. Pseudo-Differential 3:1 Multiplexer
Configuration
The
reference.
digital-to-analog
voltage at the REF
OUT
pin to be adjusted via the
serial
interface
in
2.44mV
operational amplifier with unity gain buffers the DAC
output voltage and drives the REF
OUT
pin.
The ADS7863 offers a serial interface that is
compatible with the
ADS7861
. However, instead of
the A0 pin of the ADS7861 that controls the channel
selection, the ADS7863 offers a serial data input
(SDI) pin that supports additional functions described
in the
Digital
section of this data sheet.
ADS7863
also
includes
reference
converter
a
2.5V
internal
10-bit
The
drives
a
C1
0
0
1
C0
0
1
1
ADC+
CHx0+
CHx1–
CHx1+
ADC–
CHx0–
CHx0–
CHx0–
(DAC),
allowing
the
steps.
A
low-noise
Each of the of 2pF sample-and-hold capacitors
(shown as C
S
in the
Equivalent Input Circuit
) is
connected via switches to the multiplexer output.
Opening the switches holds the sampled data during
the
conversion
process.
conversion, both capacitors are pre-charged for the
duration of one clock cycle to the voltage present at
the REF
IN
pin. After the pre-charging, the multiplexer
outputs are connected to the sampling capacitors
again. The voltage at the analog input pin is usually
different from the reference voltage; therefore, the
sample
capacitors
must
one-half
LSB
for
12-bit
acquisition
time
t
ACQ
Characteristics
).
After
finishing
the
be
charged
accuracy
(see
to
within
the
Timing
during
the
Each ADC is fed by an input multiplexer; see
Figure 15
. Each multiplexer is either used in a
fully-differential 2:1 configuration (as described in
Table 1
) or a pseudo-differential 3:1 configuration (as
shown
in
Table
2
).
The
performed using bits C1 and C0 in the SDI Register
(see also the
Serial Data Input
section).
Acquisition time is indicated with the BUSY signal
being held low. It starts by closing the input switches
(after
finishing
the
previous
pre-charging) and finishes with the rising edge of the
CONVST signal. If the ADS7863 operates at full
speed, the acquisition time is typically 125ns.
conversion
and
channel
selection
is
The input path for the converter is fully differential
and provides a common-mode rejection of 80dB at
50kHz. The high CMRR also helps suppress noise in
harsh industrial environments.
The
operational amplifier can be calculated as shown in
Equation 1
, with
n
= 12 being the resolution of the
ADS7863:
minimum
–3dB
bandwidth
of
the
driving
11
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