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參數(shù)資料
| 型號： | ADS7812UB |
| 英文描述： | Low-Power, Serial 12-Bit Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 低功耗，串行12位采樣模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 381K |
| 代理商： | ADS7812UB |
9
ADS7812
BINARY TWO’S COMPLEMENT
DIGITAL OUTPUT
TABLE III. Ideal Input Voltage and Corresponding Digital Output for Two Common Input Ranges.
DESCRIPTION
ANALOG INPUT
Full-Scale Range
Least Significant Bit (LSB)
±
10V
4.88mV
0.5V to 4.5V
0.98mV
BINARY CODE
HEX CODE
+Full Scale –1LSB
Midscale
Midscale –1LSB
–Full Scale
9.99512V
0V
–4.88mV
–10V
4.49902V
2.5V
2.49902 V
0.5V
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
7FF
000
FFF
800
FIGURE 3. Block Diagram of the ADS7812’s Digital Inputs and Outputs.
READING DATA
The ADS7812’s digital output is in Binary Two’s Comple-
ment (BTC) format. Table III shows the relationship be-
tween the digital output word and the analog input voltage
under ideal conditions.
Figure 3 shows the relationship between the various digital
inputs, digital outputs, and internal logic of the ADS7812.
Figure 4 shows when the internal shift register of the
ADS7812 is updated and how this relates to a single conver-
sion cycle. Together, these two figures point out a very
important aspect of the ADS7812: the conversion result is
not available until after the conversion is complete. The
implications of this are discussed in the following sections.
FIGURE 4. Timing of the Shift Register Update.
Q
D
S0
Q
Update of the shift
register occurs just prior
to BUSY Rising
(1)
D
S1
Q
D
S2
Q
D
S10
Q
D
S11
Q
Shift Register
Working Register
Converter Core
D
SOUT
Q
D
W0
Q
Each flip-flop in the
working register is
latched as the
conversion proceeds
D
W1
Q
D
W2
Q
D
W10
Q
D
W11
Delay
DATA
BUSY
DATACLK
CDAC
Control Logic
Clock
REF
EXT/INT
CONV
CS
NOTE: (1) If EXT/INT is HIGH (external clock), DATACLK is HIGH, and CS is LOW
during this time, the shift register will not be updated and the conversion result will be lost.
CONV
t
6
– t
25
t
25
BUSY
NOTE: Update of the internal shift register occurs in the
shaded region. If EXT/INT is HIGH, then DATACLK
must be LOW or CS must be HIGH during this time.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7812UB/1K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power Serial 12-Bit Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7812UB/1KE4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power Serial 12-Bit Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7812UB/1KG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Pwr Serial 12B Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7812UBE4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Power Serial 12-Bit Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7812UBG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Pwr Serial 12B Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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