參數(shù)資料
型號: ADS7812UB
英文描述: Low-Power, Serial 12-Bit Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述: 低功耗,串行12位采樣模擬到數(shù)字轉(zhuǎn)換器
文件頁數(shù): 8/17頁
文件大小: 381K
代理商: ADS7812UB
8
ADS7812
Convert
Convert
Acquire
Acquire
MODE
BUSY
CONV
t
3
t
2
t
1
t
5
t
4
t
7
t
6
t
8
t
10
t
11
t
9
FIGURE 2. Basic Conversion Timing.
SYMBOL
DESCRIPTION
MIN
TYP
MAX UNITS
t
1
t
2
Conversion Plus Acquisition Time
25
μ
s
μ
s
CONV LOW to All Digital
Inputs Stable
8
t
3
t
4
CONV LOW to Initiate a Conversion
40
ns
BUSY Rising to Any Digital
Input Active
0
ns
t
5
CONV HIGH Prior to Start
of Conversion
2
μ
s
t
6
t
7
t
8
t
9
t
10
BUSY LOW
15
20
μ
s
ns
CONV LOW to BUSY LOW
85
120
Aperture Delay
40
ns
Conversion Time
14
20
μ
s
μ
s
Conversion Complete to
BUSY Rising
1.1
2
t
11
t
12
Acquisition Time
5
μ
s
μ
s
CONV LOW to Rising Edge
of First DATACLK
1.4
t
13
t
14
t
15
t
16
Internal DATACLK HIGH
250
350
500
ns
Internal DATACLK LOW
600
760
875
ns
μ
s
ns
Internal DATACLK Period
1.1
DATA Valid to Internal
DATACLK Rising
20
t
17
Internal DATACLK Falling
to DATA Not Valid
400
ns
t
18
Falling Edge of Last DATACLK
to BUSY Rising
800
ns
t
19
External DATACLK Rising
to DATA Not Valid
15
ns
t
20
External DATACLK Rising
to DATA Valid
55
85
ns
t
21
t
22
t
23
t
24
External DATACLK HIGH
50
ns
External DATACLK LOW
50
ns
External DATACLK Period
100
ns
CONV LOW to External
DATACLK Active
120
ns
t
25
External DATACLK LOW
or CS HIGH to BUSY Rising
2
μ
s
t
26
t
27
CS LOW to Digital Outputs Enabled
85
ns
CS HIGH to Digital Outputs Disabled
85
ns
TABLE II. ADS7812 Timing. T
A
= –40
°
C to +85
°
C.
STARTING A CONVERSION
If a conversion is not currently in progress, a falling edge on
the CONV input places the sample and hold into the hold
mode and begins a conversion, as shown in Figure 2 and
with the timing given in Table II. During the conversion, the
CONV input is ignored. Starting a conversion does not
depend on the state of CS. A conversion can be started once
every 25
μ
s (40kHz maximum conversion rate). There is no
minimum conversion rate.
Even though the CONV input is ignored while a conversion
is in progress, this input should be held static during the
conversion period. Transitions on this digital input can
easily couple into sensitive analog portions of the converter,
adversely affecting the conversion results (see the Sensitiv-
ity to External Digital Signals section of this data sheet for
more information).
Ideally, the CONV input should go LOW and remain LOW
throughout the conversion. It should return HIGH sometime
after BUSY goes HIGH. In addition, it should be HIGH
prior to the start of the next conversion for a minimum time
period given by t
5
. This will ensure that the digital transition
on the CONV input will not affect the signal that is acquired
for the next conversion.
An acceptable alternative is to return the CONV input HIGH
as soon as possible after the start of the conversion. For
example, a negative going pulse 100ns wide would make a
good CONV input signal. It is strongly recommended that
from time t
2
after the start of a conversion until BUSY rises,
the CONV input should be held static (either HIGH or
LOW). During this time, the converter is more sensitive to
external noise.
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