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參數(shù)資料
| 型號： | ADS7810 |
| 英文描述： | 12-Bit 800kHz Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| 中文描述： | 12位800kHz采樣CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 208K |
| 代理商： | ADS7810 |
ADS7810
7
STARTING A CONVERSION
The combination of CS (pin 24) and R/C (pin 23) LOW for
a minimum of 40ns puts the sample/hold of the ADS7810 in
the hold state and starts a conversion. BUSY (pin 25) will go
LOW and stay LOW until the conversion is completed and
the internal output register has been updated. All new
convert commands during BUSY LOW will be ignored.
The ADS7810 will begin tracking the input signal at the end
of the conversion. Allowing 1.25
μ
s between convert com-
mands assures accurate acquisition of a new signal. Refer to
Table I for a summary of CS, R/C, and BUSY states and
Figures 2 and 3 for timing parameters.
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If it is critical that CS or R/C initiate
the conversion, be sure the less critical input is LOW at least
10ns prior to the initiating input.
CS
R/C
BUSY
OPERATION
1
↓
X
X
None. Databus in Hi-Z state.
0
1
Initiates conversion. Databus remains in
Hi-Z state.
0
↓
1
Initiates conversion. Databus enters Hi-Z
state.
0
1
↑
Conversion completed. Valid data from
the most recent conversion on the databus.
↓
1
1
Enables databus with valid data from the
most recent conversion.
↓
1
0
Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is
completed
0
↑
0
Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is
completed
0
0
↑
Conversion completed. Valid data from the
most recent conversion in the output
register, but output pins D11-D0 are tri-stated.
X
X
0
New convert commands ignored. Conversion
in progress.
BASIC OPERATION
Figure 1 shows a basic circuit to operate the ADS7810.
Taking R/C (pin 23) LOW for a minimum of 40ns will
initiate a conversion. BUSY (pin 25) will go LOW and stay
LOW until the conversion is completed and the output
registers are updated. Data will be output in Binary Two’s
Complement with the MSB on D11 (pin 6). BUSY going
HIGH can be used to latch the data. All convert commands
will be ignored while BUSY is LOW.
The ADS7810 will begin tracking the input signal at the end
of the conversion. Allowing 1.25
μ
s between convert com-
mands assures accurate acquisition of a new signal.
Table I. Control Line Functions for ‘read’ and ‘convert’.
FIGURE 1. Basic Operation
DESCRIPTION
ANALOG VALUE
DIGITAL OUTPUT
Full Scale Range
±
10V
4.88mV
Least Significant
Bit (LSB)
BINARY CODE
HEX CODE
+Full Scale
(10V – 1LSB)
9.995V
0111 1111 1111
7FF
Midscale
0V
0000 0000 0000
000
One LSB below
Midscale
–4.88mV
1111 1111 1111
FFF
–Full Scale
TABLE II. Ideal Input Voltages and Output Codes.
–10V
1000 0000 0000
800
BINARY TWO'S COMPLEMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7810
50
±10V
–5V
+5V
0.1μF
NC
10μF
+
+
+
0.1μF
10μF
Convert Pulse
BUSY
40ns min
D0 (LSB)
D1
D2
D3
D6
D5
D4
D7
D8
D9
D10
D11 (MSB)
0.1μF 10μF
+
+
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