參數(shù)資料
型號(hào): ADS62P45IRGCR
廠商: Texas Instruments
文件頁數(shù): 3/78頁
文件大?。?/td> 0K
描述: IC ADC 14BIT SER/PAR 125M 64VQFN
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)差分,單極
E
O
Input
Clock
CLKOUTM
CLKOUTP
Output Data
DXP, DXM
DDR
LVDS
N–10
N–9
N–1
N
N+1
N+2
N–9
N–10
N
N+2
CLKOUT
Output Data
D0–D13
Parallel
CMOS
Input
Signal
Sample
N
N+1
N+2
N+3
N+4
t
h
t
PDI
t
a
t
su
t
h
t
PDI
CLKM
CLKP
N+14
N+15
N+16
t
su
E – Even Bits D0,D2,D4,D6,D8,D10,D12
O – Odd Bits D1,D3,D5,D7,D9,D11,D13
N+1
N–1
14 Clock Cycles
(1)
14 Clock Cycles
(1)
E
T0106-04
Input
Clock
Output
Clock
Output
DataPair
CLKM
CLKOUTM
Dn_Dn+1_P,
Dn_Dn+1_M
CLKP
t
PDI
t
h
t
h
t
su
t
su
CLKOUTP
(1)
Dn
– BitsD0,D2,D4,D6,D8,D10,D12
(2)
Dn+1 – BitsD1,D3,D5,D7,D9,D11,D13
Dn
(1)
Dn+1
(2)
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
(1)
Latency is 10 clock cycles in low-latency mode.
Figure 1. Latency
Figure 2. LVDS Mode Timing
Copyright
2007–2012, Texas Instruments Incorporated
11
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