參數(shù)資料
型號: ADS62P45IRGCR
廠商: Texas Instruments
文件頁數(shù): 16/78頁
文件大?。?/td> 0K
描述: IC ADC 14BIT SER/PAR 125M 64VQFN
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個差分,單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
Table 13.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
<OUTPUT
<REF>
<OVRD>
INTERFACE
>
<COARSE GAIN>
<POWER DOWN
14
0
Internal / External
MODES
>
Over-ride bit
LVDS or CMOS
3.5 dB gain
reference
interface
D2-D0
<POWER DOWN MODES>
000
Normal operation
001
Channel A output buffer disabled
010
Channel B output buffer disabled
011
Channel A and B output buffers disabled
100
Global power down
101
Channel A standby
110
Channel B standby
111
Multiplexed mode, MUX
– (only with CMOS interface)
Channel A and B data is multiplexed and output on DB13 to DB0 pins.
D3
<REF> Reference mode
0
Internal reference enabled
1
External reference enabled
D4
<COARSE GAIN> Coarse gain control
0
0 dB coarse gain
1
3.5 dB coarse gain
D5
<OUTPUT INTERFACE> Output interface selection
0
Parallel CMOS data outputs
1
DDR LVDS data outputs
D7
<OVRD> Over-ride bit – the LVDS/CMOS selection, power down and MUX modes can also be controlled using parallel pins.
By setting
<OVRD> = 1, register bits LVDS <CMOS> and <POWER DOWN MODES> will over-ride the settings of the
parallel pins.
0
Disable over-ride
1
Enable over-ride
Table 14.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
DATA FORMAT
>
16
0
Bit / Byte wise (LVDS only)
<TEST PATTERNS>
2s complement or straight binary
Copyright
2007–2012, Texas Instruments Incorporated
23
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