參數(shù)資料
型號(hào)： ADS62P44IRGCR
廠商： Texas Instruments
文件頁(yè)數(shù)： 53/78頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT SER/PAR 105M 64VQFN
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 14
采樣率（每秒）： 105M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤(pán)（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 2 個(gè)差分，單極
CLKOUTP
CLKOUTM
DA0P
DA0M
DA2P
DA2M
OutputClock
DataBitsD0,D1
DataBitsD2,D3
Pins
DA12P
DA12M
DataBitsD12,D13
14-BitChannel-A
Data
LVDSBuffers
DB0P
DB0M
DB2P
DB2M
DataBitsD0,D1
DataBitsD2,D3
DB12P
DB12M
DataBitsD12,D13
14-BitChannel-B
Data
B0288-01
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
CMOS Mode Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital current due to CMOS output switching = CL × DRVDD × (N × FAVG),
where CL = load capacitance, N × FAVG = average number of output bits switching.
Figure 81 shows the current with various load capacitances across sampling frequencies at 2 MHz analog input
frequency.
DDR LVDS Interface
The LVDS interface works only with 3.3-V DRVDD supply. In this mode, the 11 data bits of each channel and a
common output clock are available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits
are multiplexed and output on each LVDS differential pair every clock cycle (DDR
– Double Data Rate,
Figure 95. DDR LVDS Outputs
Odd data bits D1, D3, D5, D7, D9 are output at the falling edge of CLKOUTP and even data bits D0, D2, D4, D6,
D8, D10 are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be
used to capture all the data bits.
Copyright
2007–2012, Texas Instruments Incorporated
57
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ADS62P44IRGCRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC DUAL 14B 105MSPS Para ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS62P44IRGCT 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 14B 105MSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS62P44IRGCTG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC DUAL 14B 105MSPS Para ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS62P44RGC 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs
ADS62P45 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs
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