參數(shù)資料
型號(hào): ADS62P44IRGCR
廠商: Texas Instruments
文件頁數(shù): 48/78頁
文件大?。?/td> 0K
描述: IC ADC 14BIT SER/PAR 105M 64VQFN
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 14
采樣率(每秒): 105M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)差分,單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
COARSE GAIN AND PROGRAMMABLE FINE GAIN
ADS62P4X includes gain settings that can be used to get improved SFDR performance (over 0dB gain mode).
For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 20.
The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The
fine gain is programmable in 0.5 dB steps from 0 to 6 dB; however the SFDR improvement is achieved at the
expense of SNR. So, the programmable fine gain makes it possible to trade-off between SFDR and SNR. The
coarse gain makes it possible to get best SFDR but without losing SNR significantly.
The gains can be programmed using the serial interface (bits COARSE GAIN and FINE GAIN). Note that the
default gain after reset is 0 dB.
Table 20. Full-Scale Range Across Gains
GAIN, dB
TYPE
FULL-SCALE, VPP
0
Default after reset
2V
3.5
Coarse (fixed)
1.34
0.5
1.89
1.0
1.78
1.5
1.68
2.0
1.59
2.5
1.50
3.0
1.42
Fine (programmable)
3.5
1.34
4.0
1.26
4.5
1.19
5.0
1.12
5.5
1.06
6.0
1.00
CLOCK INPUT
The clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with little or
no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using
internal 5-k
resistors as shown in Figure 90. This allows using transformer-coupled drive circuits for sine wave
clock or ac-coupling for LVPECL, LVDS clock sources (Figure 92 and Figure 93).
52
Copyright
2007–2012, Texas Instruments Incorporated
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