參數(shù)資料
型號: ADS62P44IRGCR
廠商: Texas Instruments
文件頁數(shù): 14/78頁
文件大小: 0K
描述: IC ADC 14BIT SER/PAR 105M 64VQFN
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 14
采樣率(每秒): 105M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個差分,單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
DESCRIPTION OF SERIAL REGISTERS
Table 8.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
<RST>
<SERIAL
00
0
READOUT
>
Software Reset
D1
<RST>
0
Software reset applied
– resets all internal registers and self-clears to 0.
D0
<SERIAL READOUT>
0
Serial readout disabled. SDOUT pin is forced low or high by the device ( and not put in high-impedance state)
1
Serial readout enabled, SDOUT functions as serial data readout pin.
Table 9.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
10
<CLKOUT STRENGTH>
0
D7
–D6
01
WEAKER than default drive
00
DEFAULT drive strength
11
STRONGER than default drive strength (recommended for load capacitances
> 5 pF)
10
MAXIMUM drive strength (recommended for load capacitances
> 5 pF)
Table 10.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
LVDS CURRENT
> LVDS
<CURRENT DOUBLE>
11
0
buffer current
DATAOUT STRENGTH
>
LVDS buffer current double
programmability
D1
–D0
01
WEAKER than default drive
00
DEFAULT drive strength
11
STRONGER than default drive strength (recommended for load capacitances
> 5 pF)
10
MAXIMUM drive strength (recommended for load capacitances
> 5 pF)
D3
–D2
<LVDS CURRENT> LVDS Current programmability
00
3.5 mA
01
2.5 mA
10
4.5 mA
11
1.75 mA
D5
–D4
CURRENT DOUBLE
> LVDS Current double control
00
Default current, set by
<LVDS CURR>
01
LVDS clock buffer current is doubled, 2x
<LVDS CURR>
10
LVDS data and clock buffers current are doubled, 2x
<LVDS CURR>
11
Unused
Copyright
2007–2012, Texas Instruments Incorporated
21
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