參數(shù)資料
型號(hào)： ADS62P42IRGCTG4
廠商： Texas Instruments
文件頁數(shù)： 68/78頁
文件大?。?/td> 0K
描述： IC ADC 14BIT SER/PAR 65M 64VQFN
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 14
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)差分，單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
REVISION HISTORY
Changes from Revision A (February 2008) to Revision B
Page
Added Aperature delay matching to TIMING REQUIREMENTS
— LVDS AND CMOS MODES ........................................ 8
Added tSTART description to TIMING REQUIREMENTS — LVDS AND CMOS MODES ..................................................... 9
Added tDV description to TIMING REQUIREMENTS — LVDS AND CMOS MODES .......................................................... 9
Added tSTART_CHA description to TIMING REQUIREMENTS — LVDS AND CMOS MODES ............................................... 9
Added tDV_CHA description to TIMING REQUIREMENTS — LVDS AND CMOS MODES .................................................... 9
Added tSTART_CHB description to TIMING REQUIREMENTS — LVDS AND CMOS MODES ............................................... 9
Added tDV_CHB description to TIMING REQUIREMENTS — LVDS AND CMOS MODES .................................................... 9
Changed Figure 3 CMOS Mode Timing ............................................................................................................................. 12
Added Figure 4 Multiplexed Mode Timing (CMOS only) .................................................................................................... 12
Added text to USING PARALLEL INTERFACE CONTROL ONLY section description ..................................................... 13
Added voltage values to Table 4 ........................................................................................................................................ 14
Added voltage values to Table 5 ........................................................................................................................................ 14
Changed Channel A and B powered down to Power down global in Table 6 .................................................................... 14
Changed DB10 to DB0 to DB13 to DB0 inTable 6 ............................................................................................................. 14
Added Serial Register Readout section .............................................................................................................................. 17
Added SERIAL READOUT to register address 00 in Table 7 ............................................................................................ 20
Added SERIAL READOUT to register address 00 description ........................................................................................... 21
Changed register address 14, bits D2-D0 111 description from DA10 to DA0 to DB13 to DB0 pins ................................ 23
Changed pin 56 from NC to SDOUT in CMOS interface pinout ......................................................................................... 28
Changed pin 56 from NC to SDOUT and added SDOUT description in Pin Assignments (CMOS INTERFACE) ............ 29
Changed Channel A and B powered down to Global power down in Table 21 ................................................................. 55
Changed DA13 to DA0 to DB13 to DB0 in Table 21 .......................................................................................................... 55
Changed DB0-DB10 to DB0-DB13 in Multiplexed Output Mode description ..................................................................... 60
Changed DA0-DA10 to DA0-DA13 in Multiplexed Output Mode description ..................................................................... 60
Changes from Revision B (May 2009) to Revision C
Page
Changed label positions for DDR LVDS Output Data DXP, DXM in Figure 1 .................................................................... 11
Changed D3 for register 16 ................................................................................................................................................ 24
Changed pins 29, 30 and 19, 20 in CMOS interface pinout ............................................................................................... 28
Changed pins 29, 30 in Pin Assignments CMOS INTERFACE ......................................................................................... 29
Changed pins 19, 20 in Pin Assignments CMOS INTERFACE ......................................................................................... 29
Changed pins 29, 30 and 19, 20 in LVDS interface pinout ................................................................................................ 30
Changed pins 29, 30 in Pin Assignments LVDS INTERFACE ........................................................................................... 30
Changed pins 19, 20 in Pin Assignments LVDS INTERFACE ........................................................................................... 30
Changed rising edge to falling edge and falling edge to rising edge in paragraph after Figure 95. ................................... 57
70
Copyright
2007–2012, Texas Instruments Incorporated
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參數(shù)描述
ADS62P42RGC 制造商:TI 制造商全稱:Texas Instruments 功能描述:Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs
ADS62P43 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
ADS62P43EVM 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS62P43 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
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ADS62P43IRGCR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 14B 80MSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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