參數(shù)資料
型號(hào): ADS62P42IRGCTG4
廠商: Texas Instruments
文件頁數(shù): 34/78頁
文件大?。?/td> 0K
描述: IC ADC 14BIT SER/PAR 65M 64VQFN
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 250
位數(shù): 14
采樣率(每秒): 65M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)差分,單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
3
3.3
3.6
V
CMOS interface
1.65
1.8 to 3.3
3.6
V
DRVDD Output buffer supply voltage (1)
LVDS interface
3
3.3
3.6
V
ANALOG INPUTS
Differential input voltage range
2
Vpp
VIC
Input common-mode voltage
1.5
± 0.1
V
Voltage applied on VCM in external reference mode
1.45
1.5
1.55
V
CLOCK INPUT
ADS62P45
1
125
ADS62P44
1
105
Input clock sample rate, FS
MSPS
ADS62P43
1
80
ADS62P42
1
65
Sine wave, ac-coupled
0.4
1.5
LVPECL, ac-coupled
± 0.8
Input clock amplitude differential
Vpp
(VCLKP – VCLKM)
LVDS, ac-coupled
± 0.35
LVCMOS, ac-coupled
3.3
Input clock duty cycle
35%
50%
65%
DIGITAL OUTPUTS
DEFAULT
for CLOAD ≤ 5 pF and DRVDD ≥ 2.2 V
strength
MAXIMUM
Output buffer drive strength (2)
for CLOAD > 5 pF and DRVDD ≥ 2.2 V
strength
MAXIMUM
for DRVDD
< 2.2 V
strength
CMOS interface, maximum buffer
10
strength
Maximum external load capacitance from each
LVDS interface, without internal
5
CLOAD
pF
output pin to DRGND
termination
LVDS interface, with internal
10
termination
RLOAD
Differential load resistance (external) between the LVDS output pairs
100
TA
Operating free-air temperature
-40
85
°C
(1)
For easy migration to the next generation, higher sampling speed devices (
> 125 MSPS), use 1.8V DRVDD supply.
(2)
See Output Buffer Strength Programmability in application section.
4
Copyright
2007–2012, Texas Instruments Incorporated
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