參數(shù)資料
型號： ADS62P42IRGCTG4
廠商： Texas Instruments
文件頁數(shù)： 52/78頁
文件大?。?/td> 0K
描述： IC ADC 14BIT SER/PAR 65M 64VQFN
產(chǎn)品培訓模塊： Data Converter Basics
標準包裝： 250
位數(shù)： 14
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個差分，單極
DA0
DA1
DA2
DA3
DA12
DA13
CLKOUT
CMOS
OutputBuffers
14-BitChannel-A
Data
DB0
DB1
DB2
DB3
DB12
DB13
14-BitChannel-B
Data
B0287-01
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
DIGITAL OUTPUT INFORMATION
ADS62P4X provides 14-bit data per channel and a common output clock synchronized with the data. The output
interface can be either parallel CMOS or DDR LVDS voltage levels and can be selected using serial register bit
<OUTPUT INTERFACE> or parallel pin SEN.
Parallel CMOS Interface
In the CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V
(typical). Each data bit is output on separate pin as CMOS voltage level, every clock cycle (see Figure 94).
For DRVDD
> 2.2 V, it is recommended to use the CMOS output clock (CLKOUT) to latch data in the receiving
chip. The rising edge of CLKOUT can be used to latch data in the receiver, even at the highest sampling speed.
It is recommended to minimize the load capacitance seen by data and clock output pins by using short traces to
the receiver. Also, match the output data and clock traces to minimize the skew between them.
For DRVDD
< 2.2 V, it is recommended to use external clock (for example, input clock delayed to get desired
setup/hold times).
Figure 94. CMOS Output Interface
Output Buffer Strength Programmability
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of
sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made
stronger. To minimize this, ADS62P4X CMOS output buffers are designed with controlled drive strength to get
best SNR. The default drive strength also ensures wide data stable window for load capacitances up to 5 pF and
DRVDD supply voltage
>2.2 V.
To ensure wide data stable window for load capacitance
> 5 pF, there exists option to increase the output data
and clock drive strengths using the serial interface ( DATAOUT STRENGTH and CLKOUT STRENGTH). Note
that for DRVDD supply voltage
<2.2 V, it is recommended to use maximum drive strength (for any value of load
capacitance).
56
Copyright
2007–2012, Texas Instruments Incorporated
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參數(shù)描述
ADS62P42RGC 制造商:TI 制造商全稱:Texas Instruments 功能描述:Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs
ADS62P43 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
ADS62P43EVM 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS62P43 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
ADS62P43IRGC25 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 14B 80MSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS62P43IRGCR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 14B 80MSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
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