參數(shù)資料
型號: ADS5273IPFPT
英文描述: 8-Channel, 12-Bit, 70MSPS ADC with Serialized LVDS Interface
中文描述: 8通道,12位,70MSPS的ADC的串行LVDS接口
文件頁數(shù): 4/16頁
文件大?。?/td> 254K
代理商: ADS5273IPFPT
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SBAS305A JANUARY 2004 REVISED FEBRUARY 2004
www.ti.com
4
AC CHARACTERISTICS
TMIN = 40
°
C, TMAX = +85
°
C. Typical values are at TA = 25
°
C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
LVDD = 3.3V, 0.5dBFS, internal voltage reference, and 2VPP differential input, unless otherwise noted.
ADS5273
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 10MHz
85
85
85
80
90
87
80
76
87
84
77
73
70.5
70.5
70.5
70.5
70
70
70
70
11.3
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
SFDR
Spurious-Free Dynamic Range
TBD
HD2
2nd-Order Harmonic Distortion
TBD
HD3
3rd-Order Harmonic Distortion
TBD
SNR
Signal-to-Noise Ratio
TBD
SINAD
Signal-to-Noise and Distortion
TBD
ENOB
Effective Number of Bits
Crosstalk
Signal Applied to 7 Channels; Measurement Taken on the
Channel with No Input Signal
85
dBc
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at IO = 3.5mA, RLOAD = 100
, and CLOAD = 9pF. All LVDS specifications are characterized but not tested.
PARAMETER
DC SPECIFICATIONS
VOH
Output Voltage High, OUTP or OUTN
VOL
Output Voltage Low, OUTP or OUTN
VOD
Output Differential Voltage
VOS
Output Offset Voltage
RO
Output Impedance, Single-Ended
RO
Mismatch Between OUTP and OUTN
CO
Output Capacitance
VOD
VOS
Change Between 0 and 1
ISOUTP,
ISOUTN
ISOUTNP
Output Current
IXN
,
IXP
Power-Off Output Leakage
DRIVER AC SPECIFICATIONS
Clock
Clock Signal Duty Cycle
tpHLP tpLHN
or
tpHLN tpLHP
,
Differential Skew
tpDIFF[X] tpDIFF[Y]
,
Channel-to-Channel Skew(3)
tRISE/tFALL
VOD Rise Time or VOD Fall Time
ZLOAD = 100
, CI = 9pF, IO = 3.5mA
ZLOAD = 100
, CI = 9pF, IO = 4.5mA
ZLOAD = 100
, CI = 9pF, IO = 6mA
(1)Skew measurements are made at the 50% point of the transition.
(2)Skew measurements made at 0V differential (that is, the crossing of single-ended signals).
(3)Where x is any one of the parallel channels and y is any other channel.
CONDITIONS
MIN
TYP
MAX
UNITS
RLOAD = 100
±
1%; See LVDS Timing Diagram, Page 7
RLOAD = 100
±
1%
RLOAD = 100
±
1%
RLOAD = 100
±
1%; See LVDS Timing Diagram, Page 7
VCM = 1.0V and 1.4V
VCM = 1.0V and 1.4V
VCM = 1.0V and 1.4V
RLOAD = 100
±
1%
RLOAD = 100
±
1%
1340
1038
350
1.250
TBD
1475
mV
mV
mV
V
%
pF
mV
mV
925
325
1.125
375
1.275
TBD
5
25
25
3
4
Change in
VOD
Between 0 and 1
Output Short-Circuit Current
Drivers Shorted to Ground
40
mA
Drivers Shorted Together
VCC = 0V
12
10
mA
mA
6
×
ADCLK
45
50
55
%
tSKEW1
Any Differential Pair on Package(1)
50
ps
tSKEW2
Any Two Signals on Package(2)
100
ps
ZLOAD = 100
, CI = 9pF, IO = 2.5mA
400
250
200
150
ps
ps
ps
P
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