參數(shù)資料
型號: ADS5273IPFPT
英文描述: 8-Channel, 12-Bit, 70MSPS ADC with Serialized LVDS Interface
中文描述: 8通道,12位,70MSPS的ADC的串行LVDS接口
文件頁數(shù): 2/16頁
文件大?。?/td> 254K
代理商: ADS5273IPFPT
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SBAS305A JANUARY 2004 REVISED FEBRUARY 2004
www.ti.com
2
ABSOLUTE MAXIMUM RATINGS
(1)
Supply Voltage Range, AVDD
Supply Voltage Range, LVDD
Voltage Between AVSS and LVSS
Voltage Between AVDD and LVDD
Voltages Applied to External REF Pins
All LVDS Data and Clock Outputs
ADCLK Peak Input Current
Peak Total Input Current (all inputs)
Operating Free-Air Temperature Range, TA
Lead Temperature 1.6mm (1/16
from case for 10s)
(1)Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
0.3V to 3.8V
0.3V to 3.8V
0.3V to 0.3V
0.3V to 0.3V
0.3V to 2.4V
0.3V to 2.4V
. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .
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TBD
30mA
40
°
C to 85
°
C
. . . . . .
235
°
C
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
40
°
C to +85
°
C
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5273
(1)For the most current specification and package information, refer to our web site at www.ti.com.
HTQFP-80
PFP
ADS5273IPFP
ADS5273IPFP
Tray, 96
ADS5273IPFPT
Tape and Reel, 250
RECOMMENDED OPERATING CONDITIONS
ADS5273
TYP
MIN
MAX
UNIT
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
Output Driver Supply Voltage, LVDD
3.0
3.0
3.3
3.3
3.6
3.6
V
V
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL), 1/tC
Low Voltage Level Clock
High Voltage Level Clock
ADCLKP and ADCLKN Outputs (LVDS)
LCLKP and LCLKN Outputs (LVDS)(1)
Operating Free-Air Temperature, TA
(1)6
×
ADCLK.
20
70
1
2
70
420
+85
MSPS
V
V
MHz
MHz
°
C
35
210
40
REFERENCE SELECTION
MODE
INT/EXT
DESCRIPTION
2.0VPP Internal Reference
1
Default with internal pull-up.
External Reference
0
Internal reference is powered down. Common mode of external reference should be within
50mV of VCM. VCM is derived from the internal bandgap voltage.
P
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