參數(shù)資料
型號(hào)： ADRF6801ACPZ-R7
廠商： ANALOG DEVICES INC
元件分類： 調(diào)制器/解調(diào)器
英文描述： 750 MHz - 1150 MHz RF/MICROWAVE I/Q DEMODULATOR
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, CP-40-1, LFSCP_VQ, 40 PIN
文件頁(yè)數(shù)： 9/36頁(yè)
文件大?。?/td> 1034K
代理商： ADRF6801ACPZ-R7
ADRF6801
Rev. 0 | Page 17 of 36
Register 4—Charge Pump, PFD, and Reference Path
Control
With R4[2:0] set to 100, the on-chip charge pump, PFD, and
reference path control register is programmed as shown in
The charge pump current is controlled by the base charge
pump current (ICP, BASE) and the value of the charge pump
current multiplier (ICP, MULT).
The base charge pump current can be set using an internal or
external resistor (according to Bit DB18 of Register 4). When
using an external resistor, the value of ICP,BASE can be varied
according to
[]
8
.
37
250
4
.
217
Ω
,
×
=
BASE
CP
SET
I
R
The actual charge pump current can be programmed to be a
multiple (1, 2, 3, or 4) of the charge pump base current. The
multiplying value (ICP, MULT) is equal to 1 plus the value of the
DB11 and DB10 bits in Register 4.
The PFD phase offset multiplier (θPFD, OFS), which is set by Bit
DB16 to Bit DB12 of Register 4, causes the PLL to lock with a
nominally fixed phase offset between the PFD reference signal
and the divided-down VCO signal. This phase offset is used to
linearize the PFD-CP transfer function and can improve
fractional spurs. The magnitude of the phase offset is
determined by
MULT
CP
OFS
PFD
I
,
5
.
22
[deg]
ΔΦ
θ
=
Finally, the phase offset can be either positive or negative
depending on the value of the DB17 bit in Register 4.
The reference frequency applied to the PFD can be manipulated
using the internal reference path source. The external reference
frequency applied can be internally scaled in frequency by 2×,
1×, 0.5×, or 0.25×. This allows a broader range of reference
frequency selections while keeping the reference frequency
applied to the PFD within an acceptable range.
The ADRF6801 also provides a MUXOUT pin that can be
programmed to output a selection of several internal signals. The
default mode provides a lock-detect output that allows users to
verify when the PLL has locked to the target frequency. In addition,
several other internal signals can be routed to the MUXOUT pin as
described in Figure 37.
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ADRF6806ACPZ-R7 功能描述:IC QUADRATURE DEMOD 40LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 解調(diào)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 功能:解調(diào)器 LO 頻率:- RF 頻率:70MHz ~ 300MHz P1dB:-9dBm 增益:- 噪音數(shù)據(jù):6.36dB 電流 - 電源:41.5mA 電源電壓:2.7 V 封裝/外殼:28-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:28-TQFN-EP（5x5） 包裝:帶卷 (TR)
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ADRF6807 制造商:AD 制造商全稱:Analog Devices 功能描述:700 MHz to 1050 MHz Quadrature
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